Abstract: A method of using the DAT mechanism in a computer processor to extend both: 1) the native storage access authorization architecture of the processor, and 2) to enable the processor to execute programs designed to operate under different storage access architectures. An executing program (called a source program) uses "source effective addresses" (source EAs) for locating its instructions and storage operands while executing on the processor (called the target processor).

Abstract: A method of utilizing large virtual addressing in a target computer to implement an instruction set translator (1ST) for dynamically translating the machine language instructions of an alien source computer into a set of functionally equivalent target computer machine language instructions, providing in the target machine, an execution environment for source machine operating systems, application subsystems, and applications. The target system provides a unique pointer table in target virtual address space that connects each source program instruction in the multiple source virtual address spaces to a target instruction translation which emulates the function of that source instruction in the target system. The target system efficiently stores the translated executable source programs by actually storing only one copy of any source program, regardless of the number of source address spaces in which the source program exists.

Abstract: A data processing system operating under a multiprocessing hypervisor program subject to I/O interrupts during a polling interval of the hypervisor program includes one or more processors for executing the hypervisor program and host system and one or more guest systems under the hypervisor program, a storage system connected to the processor's by a bus for storing instructions, data and control information associated with the systems being executed by the processor, the storage system may be partitioned into a number of separate areas each associated with one of the concurrently operating systems, an input/output subsystem for generating I/O interrupts to the processors, apparatus for testing to determine if the system is operating in an interpretive execution mode, apparatus for determining whether a dedicated region facility is active, apparatus for testing whether an I/O enablement mask for a guest system has been set, apparatus for setting a flag if the guest system I/O enablement mask is set, apparatus

Abstract: A software-driven multiprocessor emulation system comprising a plurality of emulation processors connected in parallel in a module. One or more modules of processors comprise an emulation system. An execution unit in each processor includes a table-lookup unit for emulating any type of logic gate function. A parallel bus connects an output of each processor to a multiplexor input with every other processor in a module. Each processor embeds a control store to store software logic-representing signals for controlling operations of each processor. Also a data store is embedded in each processor to receive data generated under control of the software signals in the control store. The parallel processors on each module have a module input and a module output from each processor. The plurality of modules have their module outputs inter-connected to module inputs of all other modules. A sequencer synchronously cycles the processors through mini-cycles on all modules.

Abstract: Provides a process which identifies the language or genre of a stored or transmitted document. The process uses a plurality of Word Frequency Tables (WFTs) respectively associated with languages/genre of interest. Each WFT contains a relatively few of the most common words of one of the languages of interest. Each word code in a WFT has an associated normalized frequency of occurrence value (NFO); use of NFOs increases the language/genre detection ability of the process. A plurality of respective accumulators are associated with the plurality of WFTs. All accumulators are set to zero before identification processing starts. The language/genre identification process receives a sequence of words from an inputted document, and compares each received word to all of the words in all WFTs. Whenever a received word is found in any WFT, the process adds the word's associated NFO to a current total in the associated accumulator.

Abstract: A high-speed cache is shared by a plurality of independently-operating data systems in a multi-system data sharing complex. Each data system has access both to the high-speed cache and to lower-speed, upper-level storage for obtaining and storing data. Management logic in the shared high-speed cache is provided to meet the serialization and data coherency requirements of the data systems when sharing the high speed cache as a store-multiple cache in a multi-system environment.

Abstract: A central processor (which may be entirely contained in a single semiconductor chip), that performs vector operations using scalar machine resources. The processor incorporates multiple parallel scalar execution unit pipelines, which do not contain hardware dedicated to vector instructions, vector registers, or vector execution controls. The processor uses scalar instructions to perform vector operations if a vector mode is indicated in the processor controls.

Abstract: A method for controlling coherence of data elements sharable among a plurality of independently-operating CPCs (central processing complexes) in a multi-system complex (called a parallel sysplex) which contains sysplex DASDds (direct access storage devices) and a high-speed SES (shared electronic storage) facility. Sysplex shared data elements are stored in the sysplex DASD under a unique sysplex data element name, which is used for sysplex coherence control. Any CPC may copy any sysplex data element into a local cache buffers (LCB) in the CPC's main storage, where it has an associated sysplex validity bit. The copying CPC executes a sysplex coherence registration command which requests a SES processor to verify that the data element name already exists in the SES cache, and to store the name of the data element in a SES cache entry if found in the SES cache. Importantly, the registration command communicates to SES the CPC location of the validity bit for the LCB containing that data element copy.

Abstract: A floating point arithmetic unit that executes a single compound instruction that produces the result A+B.times.C with A, B and C being floating point numbers. Arithmetic on the exponents of A, B and C provide a normalized result of the multiplication before the addition takes place producing a normalized result of the compound instruction. The final normalized result is identical to a result that would be obtained by executing a separate instruction for the multiply, with normalized result, followed by an add instruction with a normalized result.

Abstract: A process and apparatus for revealing manufacturing defects in testpieces, such as printed circuit boards, by passing through high-intensity attenuated x-rays (above 150 Kilo-Volts) to reusable photo plates for revealing defects in the testpieces. The x-rays are angled from 35 to 50 degrees for generating images of defects within thick multilayered printed circuit boards. During exposure, a thin lead sheet is placed between the testpiece and a phosphor photographic plate on a side of the testpeice opposite the x-ray gun. The lead sheet uniformly attenuates the high-energy x-rays to the captured image before they reach the phosphor plate to avoid damage to the photographic reuse of the plate and prevent over-exposure without loss of image contrast in the phosphor photograph. The exposed phosphor plate is excited with a low energy monochromatic radiation to visually activate the latent x-ray image in the exposed plate.

Abstract: A method and system for rebuilding storage structures located within one or more structure processing facilities of a data processing system. A connection is made to a first storage structure having a name and one or more predefined characteristics. Thereafter, a second storage structure is allocated having the same name as the first structure, however, one or more of the predefined characteristics of the second structure are different than the predefined characteristics of the first structure. The second structure may be used for planned system reconfigurations or for recovery from system failures. During the rebuilding process, notification of phases of the rebuilding process are given to the active users. Further, a capability is provided for terminating the rebuilding process. In addition, a method and system for coordinating phases of user defined processing is provided.

Abstract: A data processing system is described for providing digital video information on subscriber demand, for very large video data files. The system enables rapid response to the requests by network subscribers, independent of the number of video files offered for selection. The data processing system is coupled through a data switch to a subscriber communications network.

Abstract: A control process which enables a non-supervisory "using program" (e.g. application programs) to directly interface one or more shared asynchronous hardware facilities in a computer system. Any using program may request the operating system (OS) to set up a "special environment" with an AHF during which the using program can directly issue requests to the AHF for its services. The OS sets up a session for the using program having the "special environment", which specifies restrictions on storage accesses by the AHF for accesses made on behalf of the using program--to insure system data integrity. These restrictions are not changeable by the using program. The "special environment" exists until the session is ended by the using program or by a terminating condition.

Abstract: A method and system for providing a PROGRAM CALL to a dispatchable unit's base space is described herein. A program call to a dispatchable unit's (PC to DU) base space bit is added to each entry-table entry in order to determine whether a PROGRAM CALL to a base space is to be made. Should the bit indicate that a PROGRAM CALL to a dispatchable unit's base space is to be made, then in one embodiment, the base address space number-second-table entry origin (BASTEO) and base address space number (BASN) stored in the dispatchable unit control table (DUCT) are used in identifying the base space and accessing associated control information for the identified base space. In another embodiment, the BASN stored in the DUCT is used in ASN translation to identify the base space and access the associated control information for the base space.

Abstract: A high-speed cache is shared by a plurality of independently-operating data systems in a multi-system data sharing complex. Each data system has access both to the high-speed cache and the lower-speed, secondary storage for obtaining and storing data. Management logic and the high-speed cache assures that a block of data obtained form the cache for entry into the secondary storage will be consistent with the version of the block of data in the shared cache with non-blocking serialization allowing access to a changed version in the cache while castout is being performed. Castout classes are provided to facilitate efficient movement from the shared cache to DASD.

Abstract: Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ownership) for a cache data unit until all outstanding stores have been made in the cache data unit, after which the ownership may be changed. An ownership change may be signalled by a cross-invalidate (XI) signal to a processor. Outstanding stores are received by the pipeline after the stores are completed by a processor, and the outstanding stores output from the pipeline into a store-in cache. A continuous flow of stores is enabled into and out of the pipeline to expedite a change of ownership requested of a data unit in the cache. The continuous flow avoids having to stop a processor from putting stores into the pipeline and avoids forcing all outstanding stores out of the pipeline into the cache before indicating a change of processor ownership.

Abstract: A method and system for managing information in a data processing system is provided. The data processing system includes one or more operating systems coupled to a coupling facility. Stored within the coupling facility is data, which is accessed by one or more users. The status of those users are also stored in the coupling facility. A number of operating system services are provided for recording the users' status and managing the data and the users of the data. The data may include cache, list and/or lock structures.

Abstract: A shared fixed block architecture direct access storage system and method for use with a plurality of computer systems is described. The storage system includes a shared fixed block architecture direct access storage device with a plurality of shared files. A shared fixed block architecture control unit is coupled to the shared fixed block architecture direct access storage device and to the plurality of computer systems. The shared fixed block architecture control unit also includes a data unit responsible for moving data between a shared fixed block architecture direct access storage device in the computer systems, a SETL unit responsible for processing access requests and for creating control files corresponding to each shared file, and a heart beat unit responsible for updating the control files.

Abstract: Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does not move through MS. ES and MS are plural electronic storage media in a data processing system, and the I/O device is any I/O device selectable by the system. Intermixing of data transfers between ES and MS may be controlled by a single IDAW list accessed by a channel control word (CCW) in a channel program in a data transfer direction indicated in the CCW without any channel mode change.

Abstract: Provides load balancing, recovery and reconfiguration control for a data move subsystem comprised of a plurality of interconnected and cooperating data move processors (DMPs). Each DMP processor has an associated queue for receiving queue elements (QEs) from central processing units of a data processing system which specify data move requirements of the data processing system. QEs can be transferred between queues of other DMPs or a common queue to achieve load balancing, recovery and reconfiguration control.