Abstract: Storage is managed in a shared electronic store (SES) by assigning storage classes (STCs) to each directory entry having a data item stored in SES. The assignments of directory entries and data elements to the respective STCs can be changed at any time by any CPC. Eventually, no free space remains in the SES cache, and then space for new directory entries and data items must be obtained by reclaiming space occupied by directory entries and associated unchanged data items. The reclaiming of SES space is controlled on a STC basis. Any specified STC may reclaim from itself or from another STC using reclaiming software/microcode in SES, which includes a reclaim vector, a reclaim counter, a queue, and reclaiming controls. The vector and counter have respective elements for all possible STCs to controls how a specified STC may reclaim space from any or all target STC. Any enabled target STC reclaims its space according to an LRU algorithm maintained by a queue for the STC.

Abstract: Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction.

Abstract: This invention involves reconfiguration support for shared I/O resources in a a computer electronic complex (CEC) supporting both shared and unshared I/O channels of the type described and claimed in U.S. patent application Ser. No. 07/898,867 (PO9-92-016) filed on the same day as the subject application and assigned to the same assignee as the subject application. Prior channel subsystem call (CHSC) instructions cannot execute when a channel is to be configured as shareable by plural operating systems in a CEC.

Abstract: One or more central processing complexes (CPC's), each with one or more programs being executed, issue commands to a structured electronic storage (SES). The commands include ones that create or delete data structures in SES, and attach or detach users to the data structures. The commands include a comparative authority value operand and a new authority value operand. A data structure or user control information has an associated existing authority value. If the comparative authority value matches the existing authority value, the existing authority value is replaced by the new authority value, and the command is executed. If there is a mismatch, the existing authority value is returned to the program that issued the command, and the command is not executed in SES. This enables software to serialize management of SES and maintain a consistent view of objects in SES in the presence of faulty CPC's, without causing correctly operating CPC's to experience errors or undue delays.

Abstract: A servo-feedback method with elements for dynamically aligning a pair of mating ends of optical fibers supported in a pluggable connector. At least one of the mating ends in the pair receives light from the other mating end. The light-receiving end is mechanically vibrated (dithered) by a piezo-electric driving element relative to the other mating end in the pair to dither modulate the light passing to the receiving end. The dither modulation on the dither modulated light is electrically detected and processed relative to a dither reference wave using an analog-to-digital converter and a processor method. The detected dither modulation presents a unique waveform, in which a frequency doubling effect occurs in both half cycles of the dither reference waveform whenever the mating ends dither about their steady-state aligned position, and no dynamic error signal is then generated.

Abstract: Ziv-Lempel-type compression and expansion using separate static compression and expansion dictionaries as opposed to a single adaptive dictionary. The static dictionaries make random access processes usable for short data records instead of only long sequential data streams. Degree of compression and compression performance are improved by allowance of multiple extension characters per node and multiple children, of the same parent, that have the same first extension character. Performance is further improved by searching for matches on children of a parent and detecting a last possible match by means of fields in the parent instead of by accessing the children. Expansion performance is improved by representing in an entry not only the extension character or characters of the entry but also those of some number of ancestors of the entry, thus avoiding accessing the ancestors.

Abstract: Virtual addressing is available to a co-processor to asynchronously control the movement of multiple page units of data between different locations in the same or a different media, e.g. main store (MS) and expanded store (ES), or both may be in ES, or both may be in MS. The co-processor controls the asynchronous page movement in parallel with continuing execution of other instructions by the central processor (CP) which requested the page movement. Each page to be moved is specified by an MSB (Move Specification Block). A set of MSBs are addressed by a special type of channel control word (CCW) in a channel program containing one or more CCWs, some of which may address one or more sets of MSBs (one MSB set per CCW) to control the movement of any number of pages. The CPU executes a special ADM SSCH (start subchannel) instruction that passes the page move work to the co-processor to perform the requested page transfer involving one or more sets of MSBs.

Abstract: An addressing method using large addresses in a guest/host environment within a computer system. The guests are operating-systems, and the host is a hypervisor program. Each guest has a guest real address space (guest RAS) mapped onto a host large real address space (host LRAS) using means disclosed herein. To do this, each guest RAS is first assigned to a contiguous part of a host large virtual address space (LVAS) by assigning each guest RAS to one or more contiguous units of virtual addressing in the host LVAS, each unit having a 2 gigabyte (GB) size. The host LVAS is represented by a sequence of entries (ALEs) in a host access list (AL), in which each ALE represents a 2 GB unit of virtual addressing in the host LVAS. An ALE is selected in the AL by using a high-order part of a host large virtual address (host LVA) representing a guest RA or LRA. A host LVA is generated from a guest RA for obtaining the guest address in host main storage.

Abstract: Describes novel methods for compressing data character strings into "storage optimized indices" (SOIs) and stores their adaptive Ziv Lempel (AZL) indices, called "evolution based indices" (EBIs), in fields in corresponding entries in a SOI dictionary. The method also compresses data using the SOI dictionary, which accesses the corresponding EBIs for representing the compressed data. The EBIs are put into storage, or transmitted to a receiving location. Greater data compression processing efficiency is obtained by using the SOI dictionary than is available using prior types of AZL dictionaries. The disclosure further describes methods for decompressing EBI indices into corresponding phrases at a receiving location using either a conventional AZL dictionary or a SOI dictionary after translating received EBIs into SOIs. Also described is a submethod for phrase length determination for use in the decompression process.

Abstract: Describes a process for applying non-destructive cyclical mechanical stress to planar items in order to simulate the effects of cyclical thermal stresses. Latent defects are accelerated and screened early in a manufacturing process.

Abstract: A computer I/O system which includes a dynamic switch having a plurality of ports and a plurality of link-level facilities, with each link-level facility being attached to an individual one of the ports. Whenever the state of a port or its attached link-level facility is changed in such a way that the attached link-level facility's ability to communicate with another link-level facility might be affected, this fact is recognized by a dynamic switch control unit which causes a state change notification (SCN) frame to be transmitted to all other link-level facilities which might be affected. The link-level facilities receiving such a state change notification then determine if any of the associations or potential associations with the link-level facility which caused the state change notification are affected.

Abstract: Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.

Abstract: Provides a method for increasing the connectivity of I/O resources to a multiplicity of operating systems (OSs) running in different resource partitions of a computer electronic complex (CEC) to obtain sharing of the I/O resources among the OSs of the CEC, including channels, subchannels (devices), and control units (CUs). The invention provides image identifiers (IIDs) for assigning resources to the different OSs. Each shared I/O resource has a sharing set of control blocks (CBs) in which a respective CB is assigned to (and located by) a respective IID of one of the OSs. Each of the CBs in a sharing set provides a different image of the same I/O resource. The different CB images are independently set to different states by I/O operations for the different OSs, so that the OSs can independently share the same I/O resource.

Abstract: Enables a large number of pluggable-array connectors to be used with a multi-chip module (MCM) by using a connector technique that does not require a significant amount of available surface area on a module. The array connectors provide a large increase in the input/output (I/O) capacity of a module. Each of the connectors has a receptacle supported by a frame around the module, and short flexible transmission lines connect the receptacle to the module. A plug connects a cluster (array) of external transmission lines, which may be optical and/or electrical transmission lines operating in parallel. Optical transmission lines may have optical/electrical transducers mounted on either the frame or module. Frame mounting of optical transducers with a connector receptacle enables a connector to transfer only electrical signals between the connector and the module, regardless of a mix of optical and electrical transmission lines to the same connector plug.

Abstract: Logical erasure is done for a virtual page unit of storage in a virtual-page-initialization process (even though the data content of a backing page frame is not physically erased). Pre-initialization controls are associated with each virtual page by a pre-initialization field in each page table entry (PTE). The pre-initialization controls operate differently for fetches and stores within the address translation process. Both fetches and stores test for a pre-initialization state in an F field in the PTE to control if and when any backing page frame can be accessed. While the F field bit is set to its pre-initialization state, no erasure writing is done in any backing page frame for a fetch or full-page store operation. An optional form identifier (form#) field is associated with the pre-initialization state field. The form# field content identifies one of plural form functions or form page frames.

Abstract: Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions.

Abstract: A data processing system operated with multiple levels of virtual machine guests under a host control program. The second level of guests are invoked, operated, and terminated without host intervention, as has been required in prior systems, to significantly increase the operating efficiency of the system. Address translation is done by providing machine capability to translate second level guest addresses to real memory addresses taking advantage of the first level guest being located at a simple offset within real memory. Special facilities for second level guests periodically test for timing interruptions for second level guests and update the second level guest timing facilities.

Abstract: A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results.

Abstract: Provides a software-to-software interface and a software-to-hardware interface between software users and a hardware ADM facility (ADMF) in a data processing system. Such software user presents only virtual addresses to the software-to-software interface in a MSB list. The user list defines virtual address spaces, including a "hiperspace", in a manner that represents physical backing media as different random-access electronic storages, such main storage (MS) and expanded storage (ES). The real data transfers are within or between the backing storages. The user list is transformed into an ADM operation block (AOB), which is assigned an ADM UCB in a UCB queue which is associated with an ADM subchannel. The software-to-hardware interface generates an ORB, containing the AOB address, as an operand of a SSCB instruction which is executed to queue the associated subchannel onto one of plural co-processor queues in the ADMF.

Abstract: Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location.