Abstract: A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.

Abstract: Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any successfully-completed instructions and without any abnormal ending being provided to the program. The continued program need not have any built-in recovery or correction code. Predetermined register contents in the failed processor are stored in predetermined storage locations by the the failing processor or by a service processor (SP) when the failing processor has not been able to store this information. The predetermined contents saved from the failed processor are defined by the system architecture for saving an interruption of a program to enable the continuation of execution of the program after restoring the contents of PSWs, CRs, FPRs, GPRs, ARs, etc. if using the ESA/370 architecture.

Abstract: The disclosure describes means for allowing the sequencing of operand fetches to deviate from the conceptual sequence specified in the program. Allowing fetch sequencing deviations may improve system performance, while not causing any deviation in program execution results. Out-of-sequence (OOS) fetching may be caused by issuing each fetch without regard to the following conditions: 1. a delay in issuance to storage (such as a delay in generating the address for a fetch request); 2. a speed up in operand data return (such as due to fetching the operand data from a store buffer in the execution unit without going to storage for the data); 3. a delay in the return of operand data (such as when a fetch request has a cache miss and its data must be obtained from the storage hierarchy); or 4. an overlap in the return of fetch data for a serializer instruction with execution of instructions preceding the serializer or data and instruction fetching for instructions following the serializer before its completion.

Abstract: A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which includes a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the swithc reverses the source and destination field and returns the packet to the sender with an error flag.

Abstract: Provides three access levels of storage key protection, comprising a supervisory level (key 0), an intermediate level of non-public and non-supervisory keys (keys 1-8, 10-15), and an unique public level (key 9). The program routines operating with a supervisory-level access key can access both the public level and the intermediate level of storage blocks. Although a program routine operating with an access key in the intermediary access level cannot access any supervisory level storage block, it can access any block assigned a public level storage key, as well as any storage block assigned the respective intermediate level key. One or more third-level public storage keys (PSKs) may be provided. A program access key using one of the PSK values can only access blocks having the same PSK value, and it cannot access blocks having any other key value.

Abstract: A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch reverses the source and destination field and returns the packet to the sender with an error flag.

Abstract: A memory structure is described as comprised of a large number of fixed-size page frames. Each page frame in the memory is spread among all chips in the memory. The size of the memory structure may be extended or expanded by adding the same type of high-capacity chip originally used to construct the memory. (The chips may be constructed of semiconductor DRAM technology.) When the memory is extended/expanded, the fixed-size page frames have their lateral dimension decreased and their length increased, in accordance with the increase in the number of chips in the memory. A shift register on each chip accommodates the moving of pages within the memory structure as the page-frame shape and the redistribution of the page frame locations in the memory are changed when the number of chips in the memory structure is changed, without requiring any change in the internal structure of the chips.

Abstract: A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE.

Abstract: The embodiment enables multiple virtual data domains to be accessible to a program executing on a processor. A data domain is a set of virtual address spaces for containing data that can be accessed by an executing program. Two types of data domains are defined by access lists, called PSAL and DUAL. Each list has entries specifying virtual address spaces accessible to an executing program. The program is located in a program address space. The program address space and each data domain are located through respective control registers. On a program call, the processor loads a control register with means to identify the PSAL data domain. The loaded control register provides the called program with immediate access to its own PSAL data domain. When the call is from a different program address space, the calling program space's PSAL data domain immediately becomes non-accessible due to overlaying in the single loading of the one control register.

Abstract: A CPU has N-1 ports for concurrently making memory requests and transferring data using a cache with M partitions. Each partition includes a cache directory partition and a corresponding cache data store partition. Each port has a Partition Look-Aside Table (PLAT). Each PLAT has multiple entries that store the most-recent valid memory requests made by its CPU port. A PLAT entry includes a cache partition identifier, a control field, and a congruence-class address for locating associated data in the identified partition. Simultaneous cache accessing in up to N-1 different partitions may be made by N-1 CPU requests have PLAT local hits. The Nth port services global cache misses. An address switch simultaneously connects the CPU requests to up to N different partitions. A PLAT "local hit" occurs when a CPU request equals PLAT valid entry, enabling immediate accessing of the requested data in the identified partition. A PLAT "miss" generates a "global" request sent to all partitions.

Abstract: The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions.

Abstract: The disclosure provides event-controlled operations for an internal hardware/softward monitor for a processor in a data processing system. It embeds and distributes in each processor at least one instrumentation table unit (ITU) and event detection circuitry to detect events and conditions for collecting event-sampled hardware signals provided in the processor hardware in which the respective ITU is embedded. Instrumentation measurement is controlled centrally in the system. Sampling of the CPU signals for recording in the ITU is done at (or a sub-multiple of) the occurrence rate of the selected event(s) in the processor. The sampled signals are recorded in the ITU. The ITUs of plural processors are asynchronously operated in a system. The event-driven monitoring circuitry may be solely provided in an ITU, or it may be superimposed on a timer-driven internal instrumentation system of the type described in U.S. Pat. No. 4,590,550 in which the ITU is shared between event and timer driven modes of operation.

Abstract: This disclosure shortens a dispatching queue by deleting those queue elements having all task blocks in a wait state. The queue has no serializing lock, so that it may be used in parallel by simultaneous requestors in a multiprocessing environment. Whenever any new or deleted element acquires a dispatchable block, a dispatchability indicator is entered for the element; and if the element is off the queue, it is then inserted into the queue in a priority order of elements in the queue. Coordinated communication is provided for all other requestors that may simultaneous access any element (whether on or off the queue) by providing special flag fields for each element that indicate: the changeable/nonchangeable state of the pointer to the next element in the queue, whether the element is on or off the queue, and an identifier of the current requestor accessing the element to possibly insert or delete the element.

Abstract: A data processing system which contains a multi-level storage hierarchy, in which the two highest hierarchy levels (e.g. L1 and L2) are private (not shared) to a single CPU, in order to be in close proximity to each other and to the CPU. Each cache has a data line length convenient to the respective cache. A common directory and an L1 control array (L1CA) are provided for the CPU to access both the L1 and L2 caches. The common directory contains and is addressed by the CPU requesting logical addresses, each of which is either a real/absolute address or a virtual address, according to whichever address mode the CPU is in. Each entry in the directory contains a logical address representation derived from a logical address that previously missed in the directory. A CPU request "hits" in the directory if its requested address is in any private cache (e.g. in L1 or L2). A line presence field (LPF) is included in each directory entry to aid in determining a hit in the L1 cache.

Abstract: The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity.

Abstract: A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

Abstract: A fast path (comprising control and data busses) directly connects between a storage element in a storage hierarchy and a requestor. The fast path (FP) is in parallel with the bus path normally provided through the storage hierarchy between the requestor and the storage element controller. The fast path may bypass intermediate levels in the storage hierarchy. The fast path is used at least for fetch requests from the requestor, since fetch requests have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path in a system to decrease the peak loads on the normal path. A requestor using the fast path makes each fetch request simultaneously to the fast path and to the normal path in a system controller element (SCE). The request through the fast path gets to the storage element before the same request through the SCE, but may be ignored by the storage element if it is busy.

Abstract: A character generator uses a first memory having a permanent resident area and an overlay area. A second memory stores patterns of all characters. The permanent resident area stores character patterns having the highest frequency of use. The overlay area is not permanent and stores a subset of character patterns known to have high frequency use, but of lesser frequency than in the permanent area. A directory is provided for accessing character patterns in the overlay area. Characters are accessed using character code points. Each character code point represented in the directory has a usage count field and an address pointer field for enabling the character to be chained in a logical sequence with the other characters in accordance with their respective frequencies of use. The directory is searched serially and the search time will be shorter for the characters having highest frequency of use. The characters are accessed in the directory by their code points.

Abstract: Accurate and repeatable time accounting is done in an asymmetric multiprocessing system (AMP) by converting the actual execution time of each dispatch of a task on a minor processor in the AMP to an equivalent execution time which would have been obtained if the dispatch had instead been on the major processor in the AMP, so that the overall task time in the AMP is independent of whether the task is dispatched on a minor processor or a major processor in the AMP. Dispatching on an AMP is made more efficient by determining an affinity value (AV) for each task. The AV is the ratio of the task's emulation time on the minor processor to the task's total dispatch time on all processors in the AMP. A low affinity value (near zero) indicates better efficiency for the task by next dispatching it on a minor processor. A high affinity value (near one) indicates better efficiency for the task by next dispatching it on a major processor. The affinity value may be based on all prior dispatches fo the task (i.e.

Abstract: A method for controlling both shared and exclusive access for a resource in a multiprocessor system wherein a first-in/first-out queue is formed for tasks suspended while awaiting access and wherein access to the resource provides that control of access required for manipulation of the first-in/first-out queue which is not provided by the atomic nature of compare (double) and swap. Each member of the queue has indicators of the access it requested and of the next most recently enqueued member which has a corresponding indicator. A lockword is established having two parts, a lock flag indicating the status of the resource, whether available, under shared ownership or under exclusive ownership and a lock pointer pointing to the most recently enqueued task. In requesting or releasing access, an initial guess is made as to the value of the lockword and a projected lockword is calculated based on the guess.