Abstract: An improved fishing system that records ambient conditions existing at or around the time a fish is caught. The fishing system includes a lure which records ambient conditions, including time, date, depth, temperature, ambient light, an underwater picture of a hooked fish and water quality. After catching a fish, the recorded data is transmitted from the lure to a handheld control unit. The handheld control unit is also capable of recording location (via GPS), fish weight, water quality, and an out-of-water picture of the fish. The data stored by the handheld control unit is transmitted (via a wireless or wired network) and recorded in an Internet database. The lure can also be controlled to release a hook that becomes irretrievably stuck in an underwater obstruction. The path of the lure in the water can also be controlled.

Abstract: The present invention provides an apparatus and method of multiple antenna receiver combining of high data rate wideband packetized wireless communication signals, where the apparatus includes M receive antennas, receiving M high data rate wideband packetized wireless communication signals, where each of the signals includes N frequency bins. The apparatus, in an exemplary embodiment, includes (1) a joint timing recovery units that perform joint coarse signal timing estimation, joint frequency offset estimation, and joint fine timing estimation on each of the signals, (2) M Fast Fourier Transform units (FFTs) that each convert the digital data for each of the M signals into frequency domain information for each of the N received frequencies and that output Q pilots for each of the signals, where Q is a positive integer, and (3) a combiner that weights and combines the outputs of the M FFTs for each of the N received frequencies.

Abstract: A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultiMediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

Abstract: A method and apparatus for routing data in a device having a plurality of parts. A signal is received at a first port. A detection is made that the first port received the signal. information contained in the signal is selectively routed from the first port to a data recovery circuit.

Abstract: An improved microvalve is described. The microvalve is formed such that the walls of the microvalve are formed from a gel material. Typically, the microvalve includes open flow paths, often holes, through a gel layer. An electric field is applied in regions where fluid flow is undesirable. The electric field compresses the gel closing the flow path thereby preventing further fluid flow.

Abstract: To provide fast mask defect scoring, approximated wafer simulations (e.g. using one convolution) are performed on the defect inspection image and its corresponding reference inspection image. Using the approximated defect wafer image and the approximated reference wafer image generated by these approximated wafer simulations, a defect maximum intensity difference (MID) is computed by subtracting one approximated wafer image from the other approximated wafer image to generate a difference image. After a defect region of the difference image is clearly defined, a simulation at the centroid (i.e. a single point) of the defect region is performed. After the defect MID is computed (represented by an intensity) it can be compared to a prototype MID, which can represent a generic nuisance defect.

Abstract: A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.

Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.

Abstract: A low-dropout voltage (LDO) regulator that creates a zero in the open loop gain using a relatively small-sized current control element to divert part of the supplied load current through a “zero” resistor before adding it to the output load. The main part of the output load is passed through a relatively large second current control element. A control signal generated by an error amplifier (e.g., an op-amp) is used to control the small current control element, but is passed through a boost zero compensating resistor before being applied to the large current control element. The voltage signal developed across the “zero” resistor mimics the magnitude and phase of a zero in the loop. This voltage signal is added to the loop gain by, for instance, using a bypass capacitor, and the resulting feedback signal is supplied to the error amplifier.

Abstract: A LED driver IC includes a control module(s) for controlling one or more LED drive parameters and non-volatile memory for storing settings data for that control module(s). The control module(s) is fully integrated into the LED driver IC and does not require any control input from off-chip components or signals. Therefore, the space requirements for LED circuits that make use of the LED driver IC can be minimized. Also, the non-volatile memory storage of settings data eliminates the need for an initialization or configuration input each time the LED driver IC is powered on. The non-volatile memory can be a one-time programmable memory or can be a reprogrammable memory.

Abstract: A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models.

Abstract: An amplifier can advantageously use a power supply voltage source that provides a voltage greater than all breakdown voltages of the process associated with transistors of the amplifier. Specifically, cascoded configurations can be used to reduce the gate-drain and source-drain voltages of “at-risk” transistors in the amplifier. During a power down mode, a bias shunt of the amplifier can isolate certain nodes from the voltage sources. At the same time, a charge circuit of the amplifier can charge those nodes to a predetermined voltage, thereby minimizing stress to the at-risk transistors during the power down mode. A multi-flavor power down signal generator circuit can advantageously generate the appropriate power down signals for driving various transistors of the amplifier during the power down mode.

Abstract: A system for detecting the level of the noise floor due to circuit noise as seen at the ADC for a wireless receiver. The system measures power after digitizing and filtering, and subtracts off any variable gain used in the analog front end to determine differentially the size of the signal at the antenna. The system further differentially detects the signal size of any incoming signal at the antenna in a similar fashion, and determines its size relative to the measured noise floor. If the level of the circuit noise of the receiver is known absolutely, the absolute signal size of the incoming signal can likewise be determined with this inventive method and system.

Abstract: A solar concentrator photovoltaic (CPV) device in which concentrator elements (optics, PV cells and wiring) are laminated to form a composite, substantially planar structure. The concentrator optics are implemented by a solid (e.g. glass) optical element that defines a focal point at which solar light received by the optical element is concentrated. Using vacuum lamination techniques, a printed circuit structure attached by way of an adhesive layer onto a surface of the optical element. The printed circuit structure includes one or more non-conductive layers and conductors that are disposed on the non-conductive layers. The PV cell is connected to printed circuit structure, and is positioned at the focal point of the optical element. Optional front and/or back protective layers are also attached prior to the lamination process. A CPV array includes multiple devices formed on an optical tile using a string-like flexible printed circuit structure.

Abstract: Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer, and a central opening that exposes a central active area of the wafer. The extrusion head is then moved relative to the wafer, and the extrusion material is continuously extruded through outlet orifices of the extrusion head to form elongated extruded structures on the active area of the wafer. The mask prevents deposition of the extrusion material along the peripheral edges of the wafer, and facilitates the formation of unbroken extrusion structures. The mask may be provided with a non-rectangular opening to facilitate the formation of non-rectangular (e.g., circular) two-dimensional extrusion patterns.

Abstract: Many areas of technology need highly accurate data compression to provide small, multifunctional devices. In the area of communication governed by the IEEE 802.11 standards, a wireless device could significantly improve its performance by using its calibration data. Moreover, because of the increased mobility of users, a wireless device should be able to operate in different regulatory domains. This flexibility requires access to significant amounts of data regarding such regulatory domains. Advantageously, piecewise linear abstraction and/or mapping can be used to significantly reduce the amount of stored data while ensuring accuracy in reproducing the total data at a later point in time.

Abstract: One embodiment of the present invention sets forth a technique for mitigating fractional spurs in fractional-n frequency synthesizer circuits. The technique involves advantageously modifying certain least significant bit values in the programming bits of the fractional-n frequency synthesizer circuit to avoid pathological fractional bit patterns. As a result, fractional spurs present in conventional fractional-n frequency synthesizer circuits may be attenuated, thereby improving the overall quality of the resulting out signal.

Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

Abstract: A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding unit decodes the transaction clump tag to recover temporal information regarding the transaction to avoid violations of the ordering rules.

Abstract: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.