Abstract: An improved fuel cell is described. The invention addresses the problem of mechanical failure in thin electrolytes. One embodiment varies the thickness of the electrolyte and positions at least either the anode or cathode in the recessed region to provide a short travel distance for ions traveling from the anode to the cathode or from the cathode to the anode. A second embodiment uses a uniquely shaped manifold cover to allow close positioning of the anode to the cathode. Using the described structures results in a substantial improvement in fuel cell reliability and performance.

Abstract: Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer, and a central opening that exposes a central active area of the wafer. The extrusion head is then moved relative to the wafer, and the extrusion material is continuously extruded through outlet orifices of the extrusion head to form elongated extruded structures on the active area of the wafer. The mask prevents deposition of the extrusion material along the peripheral edges of the wafer, and facilitates the formation of unbroken extrusion structures. The mask may be provided with a non-rectangular opening to facilitate the formation of non-rectangular (e.g., circular) two-dimensional extrusion patterns.

Abstract: A common access ring (CAR) architecture that supports multiple masters and slaves is provided. One or more masters may make a request on the ring at the same time, such that multiple transactions are simultaneously pending. Moreover, multiple masters may simultaneously make a request to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no more than one request arrives at a slave at any given time. If a request arrives while a slave is processing a previous request, the arriving request is not serviced, and the master that originated the arriving request is asked to retry the request at a later time. Atomic shadow-write operations are supported by including all shadow registers in a dedicated sub-ring of the CAR architecture.

Abstract: A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first predetermined set of queues is assigned to the first port for read operations, and a second predetermined set of queues is assigned to the second port for read operations. Data can be read from the first predetermined set of queues to the first port at the same time that data is read from the second predetermined set of queues to the second port.

Abstract: A curved spring structure includes a base section extending parallel to the substrate surface, a curved cantilever section bent away from the substrate surface, and an elongated section extending from the base section along the substrate surface under the cantilevered section. The spring structure includes a spring finger formed from a self-bending material film (e.g., stress-engineered metal, bimorph/bimetallic) that is patterned and released. A cladding layer is then electroplated and/or electroless plated onto the spring finger for strength. The elongated section is formed from plating material deposited simultaneously with cladding layers. To promote the formation of the elongated section, a cementation layer is provided under the spring finger to facilitate electroplating, or the substrate surface is pre-treated to facilitate electroless plating.

Abstract: A global node optimization (GNO) technique can generate a model for a planar multiple layer film stack structure, e.g. a binary grating structure. In this technique, after obtaining spectra and target thicknesses from one or more wafers, a continuous film approximation (CFA) and a grating factor (GF) set are identified. A model using the CFA and the GF set is optimized by simultaneously fitting a plurality of the spectra while minimizing error compared to the target thicknesses. After simultaneously fitting all of the spectra, a GNO stack is created. A GNO recipe is then created using the GNO stack. Notably, a tool implementing the GNO technique uses minimal modeling capabilities and computational resources.

Abstract: A method for extruding composite materials on a substrate includes feeding a first material into a first channel and a second material, used to maintain a shape of the first material, into one or more second channels residing on at least one side of the first channel, merging the flows of the first and second materials into a single flow in which the second material surrounds the first material, applying the single flow to a substrate to produce at least one composite material, and post-processing the composite material to form a solid.

Abstract: A dual-zone steam fuser for a xerographic system includes a ultra-heated first zone maintained at 200-500° C. that quickly heats a paper substrate to an optimal toner fusing temperature (e.g., 120-150° C.), and a second, relatively cool second zone for maintaining the substrate at the optimal temperature during completion of the fusing process. A conveying system conveys the substrate so that it exits the first zone and enters the second zone immediately after the substrate temperature reaches the optimal toner fusing temperature, and is maintained in the second zone for a predetermined fusing operation time period. The gas (e.g., steam) temperatures and timing are selected such that surface condensation is minimized during initial heating, and such that moisture content is normalized at the end of the fusing process.

Abstract: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.

Abstract: The invention teaches an amplifier (100) with an input signal (IN) coupled to the gate of a second transistor (Q2) and an output signal (OUT) coupled to an output node between a third resistor (R3) and the drain of the second transistor (Q2). A third transistor (Q3) is coupled in parallel between the output node and the gate of a second transistor (Q2). A first bias signal (Vbias) is coupled to the output node and the gate of the third transistor (Q3). The amplifier preferably also includes a plurality of switchable resistors coupled to the output node to adjust the output for process variations. The invention also describes a method of compensating for process variations in an output of an amplifier which comprises producing a reference signal dependent on the difference between a reference value and an actual value and switching one or more resistors into the output of the amplifier to adjust the output of the amplifier to reflect the process variations.

Abstract: A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.

Abstract: A radio communication device is tested by forwarding relevant signal characteristic data derived at the physical (PHY) layer to the media access control (MAC) layer for processing, analysis and feedback to the radio circuit to improve performance. The relevant signal characteristics are forwarded to the MAC within (appended to) a data packet. Thus, the relevant signal characteristic is forwarded to the MAC along an existing data path (a path originally designed to transfer the receive frame only, but now transfers the combined receive frame with the attached radio characteristic). The radio characteristic may be used for testing and/or tuning the radio circuit. In one embodiment, the radio characteristic is a frequency domain representation of a received signal. The radio is tuned based on a channel estimate derived from comparison of frequency domain representations of transmitted and received signals.

Abstract: A USB device including a housing and a protective cap that are slidably and/or pivotably connected together such that the protective cap is able to slide and/or pivot between an open position, in which a plug connector extending from the front of the housing is exposed for operable coupling to a host system, and a closed position, in which the protective cap is disposed over the front end portion of the housing to protect the plug connector. A pivoting/sliding mechanism is provided on the housing and cap that secures the protective cap to the housing at all times, including during transitional movements of the protective cap between the opened and closed positions.

Abstract: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.

Abstract: A system and method for closely synchronizing the transmission of real-time data streams is described. Synchronization data is transmitted by a cycle master for receipt by one or more cycle slaves. A cycle slave updates an internal state based on synchronization data received from the cycle master. This internal state may govern reproduction of received real-time data streams by the cycle slave. Such synchronization data may be inserted into transmitted media streams. The cycle slave internal state may be more accurately set by calculating timing differences between the cycle master and cycle slave and periodically adjusting that internal state between receipt of the synchronization data from the cycle master.

Abstract: An apparatus and method for providing electrostatic discharge protection of a transmit integrated circuit including an ESD protect block coupled to an integrated circuit pad in a package without bond wires, and an ESD clamp circuit coupled between the ESD protect block and ground. During transmission, one or more capacitors within the ESD protect block may charge up to various levels near the peak transmit voltage, which reverse biases one or more diodes in the ESD protect block, thereby buffering the transmit circuit from the capacitive load of the ESD clamp circuit. The ESD protect block may prevent the ESD clamp circuit from activating due to the high peak voltages output from the transmit circuit. An embodiment of the ESD protect block may apply particularly to transmit power amplifier circuits in which the output signal peaks at twice the supply voltage. In one embodiment applicable for lower voltage CMOS processes, the ESD protect block includes a diode and a capacitor.

Abstract: A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is a matrix suitable for parallel processing and N is a coupling matrix. M and N are then preconditioned to form M?1Jx=(I+M?1N)x=M?1r and the Jacobian matrix J is solved using an iterative solving method.

Abstract: A co-extrusion head for forming high-aspect ratio gridline structures in a micro extrusion apparatus includes multiple sheets (e.g., metal plates) that are machined and assembled to define three-part fluidic channels having associated outlet orifice disposed along an edge surface of the head. Reference surfaces are also etched in the sheets and are aligned in a straight line that intersects output junctions of the three-channel cavities. After assembly (e.g., using high pressure bonding techniques), each reference surface is located inside a notch defined in the edge surface. The edge surface of the co-extrusion head is then trimmed (e.g., machined by wire EDM) using the reference surfaces as a precise guide, thereby producing uniform length outlet orifices with uniform flow impedance.

Abstract: A color image sensor includes an array of pixels arranged in a plurality of pixel groups, each pixel group including a floating diffusion that is shared by four pixels disposed in a 2×2 arrangement. Each of said four pixels includes a photodetector and a color filter superposed over the photodetector, wherein a first pair of said four pixels include green color, and a second pair of said four pixels includes either red or blue color filters. A control circuit controls the pixel groups such that discrete image information is generated from each pixel in normal light situations, and such that summed image information is generated from each pixel group in low light situations by simultaneously connecting the green pixels to the floating diffusion during a first time period, and simultaneously connecting the red/blue pixels to said floating diffusion during a second time period.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.