Abstract: The polishing pad is suitable for planarizing at least one of semiconductor, optical and magnetic substrates. The polishing pad includes a cast polyurethane polymeric material formed with an isocyanate-terminated reaction product formed from a prepolymer reaction of a prepolymer polyol and a polyfunctional isocyanate. The isocyanate-terminated reaction product has 4.5 to 8.7 weight percent unreacted NCO; and the isocyanate-terminated reaction product is cured with a curative agent selected from the group comprising curative polyamines, curative polyols, curative alcoholamines and mixtures thereof. The polishing pad contains at least 0.1 volume percent filler or porosity.

Abstract: The invention provides a polishing pad useful for polishing at least one of semiconductor, magnetic and optical substrates. It includes a polymeric matrix having a polishing surface. Polymeric microelements are distributed within the polymeric matrix and at the polishing surface of the polymeric matrix. Silicate-containing regions distributed within each of the polymeric microelements coat less than 50 percent of the outer surface of the polymeric microelements. Less than 0.1 weight percent total of the polymeric microelements are associated with i) silicate particles having a particle size of greater than 5 ?m; ii) silicate-containing regions covering greater than 50 percent of the outer surface of the polymeric microelements; and iii) polymeric microelements agglomerated with silicate particles to an average cluster size of greater than 120 ?m.

Abstract: The method provides a method of preparing a silicate-containing polishing pad useful for polishing at least one of semiconductor, magnetic and optical substrates. The method includes introducing a feed stream of gas-filled polymeric microelements into a gas jet. The polymeric microelements have varied densities, varied wall thickness and varied particle size. Passing the gas-filled microelements in the gas jet adjacent a Coanda block, the Coanda block having a curved wall for separates the polymeric microelements with Coanda effect, inertia and gas flow resistance. The coarse polymeric microelements from the curved wall of the Coanda block to clean the polymeric microelements. The polymeric microelements collected contain less than 0.

Abstract: The polishing pad is useful for polishing at least one of magnetic, optical and semiconductor substrates. A porous polishing layer includes a dual porosity structure within a polyurethane matrix. The dual porosity structure has a primary set of pores having pore walls with a thickness of 15 to 55 ?m and a storage modulus of 10 to 60 MPa measured at 25° C. In addition, pore walls contain a secondary set of pores having an average pore size of 5 to 30 ?m. The porous polishing layer is either fixed to a polymeric film or sheet substrate or formed into a woven or non-woven structure to form the polishing pad.

Abstract: The invention provides a polishing pad useful for polishing at least one of a magnetic, optical and semiconductor substrate in the presence of a polishing medium with a polishing pad. The polishing pad comprises a center, an inner region surrounding the center, a transition region connecting grooves from the inner region to an outer region surrounding the inner region. The outer region has multiple grooves with a high-rate path. The transition region is adjacent the outer region and within a radius from the center defined as follows: r TR = 0.7 ? r * ? ? to ? ? 1.3 ? r * where r * = R C ? ( R R C ) 2 - cos ? ( 2 ? ? c ? ? 0 ) - sin ? ( 2 ? ? c ? ? 0 ) ? ( R / R C cos ? ? ? c ? ? 0 ) 2 - 1 ; with the inner region originating continuous grooves that extend uninterrupted to the outer region.

Abstract: The invention provides a method for polishing at least one of a magnetic, optical and semiconductor substrate in the presence of a polishing medium with a polishing pad. The substrate is fixed within a carrier fixture having a channel-free surface. The method comprises securing the substrate in the carrier fixture with the channel-free surface adjacent and parallel to a polishing surface of the polishing pad. The polishing pad has multiple grooves with high-rate paths. The method includes applying polishing medium to the polishing pad adjacent the carrier fixture; and rotating the polishing pad and carrier fixture to polish the substrate with the polishing pad and the polishing medium wherein the channel-free surface of the carrier fixture presses against the polishing pad to impede flow of the polishing medium into the substrate and the high-rate groove paths traverse the carrier fixture to promote flow of the polishing medium to the substrate.

Abstract: The polishing solution is useful for removing a barrier from a semiconductor substrate. The solution contains by weight percent 0.001 to 25 oxidizer, 0.0001 to 5 anionic surfactant, 0 to 15 inhibitor for a nonferrous metal, 0 to 40 abrasive, 0 to 20 complexing agent for the nonferrous metal, 0.01 to 12 barrier removal agent selected from imine derivative compounds, hydrazine derivative compounds and mixtures thereof, and water; and the solution has an acidic pH.

Abstract: The polishing method uses a polishing solution for removing barrier materials in the presence of interconnect metals and dielectrics. The polishing solution comprises, by weight percent, 0.1 to 10 hydrogen peroxide, at least one pH adjusting agent selected from the group consisting of nitric acid, sulfuric acid, hydrochloric acid and phosphoric acid for adjusting a pH level of the polishing solution to less than 3, at least 0.0025 benzotriazole inhibitor for reducing removal rate of the interconnect metals, 0 to 10 surfactant, 0.01 to 10 colloidal silica having an average particle size of less than 50 nm and balance water and incidental impurities. The polishing solution has a tantalum nitride material to copper selectivity of at least 3 to 1 and a tantalum nitride to TEOS selectivity of at least 3 to 1.

Abstract: The polishing solution is useful for removing barrier materials in the presence of at least one nonferrous interconnect metal with limited erosion of dielectrics. The solution contains 0 to 20 weight percent oxidizer, at least 0.001 weight percent inhibitor for reducing removal rate of the nonferrous interconnect metals, 1 ppm to 4 weight percent organic-containing ammonium cationic salt formed with a quanternary ammonium structure, 1 ppm to 4 weight percent anionic surfactant, the anionic surfactant having 4 to 25 carbon atoms and the total carbon atoms in of the ammonium cationic salt plus the anionic surfactant being 6 to 40 carbon atoms, 0 to 50 weight percent abrasive and balance water; and the solution having a pH of less than 7.

Abstract: The polishing pad (104) is useful for polishing at least one of magnetic, optical and semiconductor substrates (112) in the presence of a polishing medium (120). The polishing pad (104) includes a plurality of polishing elements (402, 502, 602, 702). The polishing elements (402, 502, 602, 702) are aligned in a vertical direction and having a first and a second end. A plurality of junctions (404, 510, 610, 710) connects the first and second ends of the polishing elements (402, 502, 602, 702) with at least three polishing elements at each of the plurality of junctions (404, 510, 610, 710) for forming a tier. Each tier representing a thickness in the vertical direction between the first and second ends of the polishing elements (402, 502, 602, 702). And an interconnected lattice structure (400, 600) forms from connecting sequential tiers of the plurality of junctions (404, 504) that connect the polishing elements (402, 502, 602, 702).

Abstract: A chemical mechanical polishing pad (104, 400) that includes a polishing layer (108, 420, 500) having a set of primary grooves (124, 408, 516) formed in a polishing surface (110, 428, 520) of the pad. The pad also includes a set of secondary grooves (128, 404, 504) that become selectively active as a function of the wear of the polishing layer from polishing.

Abstract: An aqueous solution is useful for selective removal in the presence of a low-k dielectric. The aqueous solution comprises by weight percent 0 to 25 oxidizer; 0.00002 to 5 multi-component surfactant, the multi-component surfactant having a hydrophobic tail, a nonionic hydrophilic portion and an anionic hydrophilic portion, the hydrophobic tail having 6 to 30 carbon atoms and the nonionic hydrophilic portion having 10 to 300 carbon atoms; 0 to 15 inhibitor for a nonferrous metal; 0 to 50 abrasive; 0 to 20 complexing agent for a nonferrous metal; and water.

Abstract: The aqueous slurry is useful for chemical mechanical polishing semiconductor substrates having copper interconnects. The aqueous slurry includes by weight percent, 0.01 to 25 oxidizing agent, 0.1 to 50 abrasive particles, 0.001 to 3 polyvinyl pyrrolidone, 0.01 to 10 inhibitor for decreasing static etch of the copper interconnects, 0.001 to 5 phosphorus-containing compound for increasing removal rate of the copper interconnects, 0.001 to 10 complexing agent formed during polishing and balance water; and the aqueous slurry has a pH of at least 8.

Abstract: The polishing pad (104) is useful for polishing at least one of magnetic, optical and semiconductor substrates (112) in the presence of a polishing medium (120). The polishing pad (104) includes a three-dimensional network of interconnected unit cells (225). The interconnected unit cells (225) are reticulated for allowing fluid flow and removal of polishing debris. A plurality of polishing elements (208, 308 and 408) form the three-dimensional network of interconnected unit cells (225). The polishing elements (208, 308 and 408) have a first end connected to a first adjacent polishing element at a first junction (209, 309 and 409) and a second end connected to a second adjacent polishing element at a second junction (209, 309 and 409) and having a cross-sectional area (222, 322 and 422) that remains within 30% between the first and the second junctions (209, 309 and 409).

Abstract: The polishing fluid is useful for polishing tantalum-containing barrier materials of a semiconductor substrate. The polishing fluid includes a nitrogen-containing compound having at least two nitrogen atoms comprising imine compounds and hydrazine compounds. The nitrogen-containing compound is free of electron-withdrawing substituents; and the polishing fluid is capable of removing the tantalum-containing barrier materials from a surface of the semiconductor substrate without an abrasive.

Abstract: A method of manufacturing polymer-coated particles is useful for chemical mechanical polishing magnetic, optical, semiconductor or silicon substrates. First it provides a dispersion of particle cores in a non-aqueous solvent. Then introducing a polymeric precursor into the dispersion to react the polymeric precursor forms a polymer. The polymer coats at least a portion of the surface of the particle cores with the polymer and forms the polymer-coated particles having a solid outer polymeric shell. Substituting the non-aqueous solvent with water forms an aqueous mixture containing the polymer-coated particles. And it forms an aqueous chemical mechanical polishing formulation with the polymer-coated particles without drying the polymer-coated particles.

Abstract: The polishing pad (104) is useful for polishing at least one of magnetic, optical and semiconductor substrates (112) in the presence of a polishing medium (120). The polishing pad (104) includes a three-dimensional network of interconnected unit cells (225). The interconnected unit cells (225) are reticulated for allowing fluid flow and removal of polishing debris. A plurality of polishing elements (208) form the three-dimensional network of interconnected unit cells (225). The polishing elements (208) have a mean height (214) to a mean width (222) ratio of at least 3. The polishing surface (200) formed from the plurality of polishing elements (208) remains consistent for multiple polishing operations.

Abstract: The polishing pad is suitable for planarizing at least one of semiconductor, optical and magnetic substrates. The polishing pad has an ultimate tensile strength of at least 3,000 psi (20.7 MPa) and polymeric matrix containing closed cell pores. The closed cell pores have an average diameter of 1 to 50 ?m and represent 1 to 40 volume percent of the polishing pad. The pad texture has an exponential decay constant, ?, of 1 to 10 ?m as a result of the natural porosity of the polymeric matrix and a surface texture developed by implementing periodic or continuous conditioning with an abrasive. The surface texture has a characteristic half height half width, W1/2 that is less than or equal to the value of ?.

Abstract: A chemical mechanical polishing pad having an annular polishing track and a concentric center O. The polishing pad includes a polishing layer having a plurality of pad grooves formed therein. The polishing pad is designed for use with a carrier, e.g., a wafer carrier, that includes a polishing ring having a plurality of carrier grooves. Each of the plurality of pad grooves has a carrier-compatible groove shape configured to enhance the transport of a polishing medium beneath the carrier ring on the leading edge of the carrier ring during polishing.

Abstract: A chemical mechanical polishing pad having an annular polishing track and a concentric center O. The polishing pad includes a polishing layer having a plurality of pad grooves formed therein. The polishing pad is designed for use with a carrier, e.g., a wafer carrier, that includes a polishing ring having a plurality of carrier grooves. Each of the plurality of pad grooves has a carrier-compatible groove shape configured to enhance the transport of a polishing medium beneath the carrier ring on the leading edge of the carrier ring during polishing.