Abstract: An aqueous composition is useful for polishing semiconductor wafers. The composition comprises a nonionic surfactant that suppresses removal rate of silicon carbide-nitride and has a hydrophilic group and a hydrophobic group. The hydrophobic group has a carbon chain length of greater than three. And the nonionic surfactant suppresses silicon carbide-nitride removal rate at least 100 angstroms per minute greater than its decrease in silicon nitride removal rate as measured with a microporous polyurethane polishing pad pressure measured normal to a wafer of 13.8 kPa.

Abstract: A chemical mechanical polishing pad (200) that includes a polishing layer (204) having a polishing region (208) and containing a plurality of grooves (212) extending at least partially into the polishing region. During polishing, the grooves contain a slurry (236) that facilitates polishing. Each groove includes a plurality of mixing structures (220) configured to cause mixing of slurry located in a lower portion (240) of the groove with slurry located in the upper portion (244) of the groove.

Abstract: An aqueous polishing composition comprises a corrosion inhibitor for limiting removal of an interconnect metal with an acidic pH. The composition includes an organic-containing ammonium salt formed with R1, R2, R3 and R4 are radicals, R1 has a carbon chain length of 2 to 15 carbon atoms. The organic-containing ammonium salt has a concentration that accelerates TEOS removal and decreases removal of at least one coating selected from the group consisting of SiC, SiCN, Si3N4 and SiCO.

Abstract: A textured surface characterization system (100) includes a characterization apparatus (110) that contacts a textured surface (104) of an item (108) in order to characterize that surface. The characterization system includes a fluid delivery system (204) for flowing a fluid (128) across the textured surface when the textured surface is in contact with the characterization apparatus. Pressure measurement structures (144, 160) on the characterization apparatus provide pressure data for the fluid as it flows across the textured surface. This pressure data is used to characterize the textured surface.

Abstract: A polishing pad (104, 300, 400, 500) for polishing a wafer (112, 516), or other article. The polishing pad includes a polishing layer (108) containing a plurality of grooves ((148, 152, 156)(304, 308, 324)(404, 408, 424)(520, 524, 528)) having orientations largely parallel to one or more corresponding respective velocity vectors (V1–V4)(V1?–V4?)(V1?–V4?)(V1??–V4??) of the wafer. These parallel orientations promote the formation of mixing wakes in a polishing medium (120) within these grooves during polishing.

Abstract: A polishing pad (104, 300, 400, 500) for polishing a wafer (112, 516), or other article. The polishing pad includes a polishing layer (108) having a polishing region (164, 320, 420, 504) defined by first and second boundaries ((168, 172), (312, 316), (412, 416) (508, 512)) having shapes and locations that are a function of the size of polished surface (116) of the article being polished and the type of polisher (100) used. The polishing region has several zones ((Z1–Z3) (Z1?–Z3?)(Z1?–Z3?)(Z1??–Z3??)) each containing corresponding grooves ((148, 152, 156)(304, 308, 324)(404, 408, 424)(520, 524, 528)) having orientations selected based on the direction of one or more velocity vectors (V1–V4)(V1?–V4?)(V1?–V4?) (V??–V4??) of the wafer in that zone.

Abstract: An aqueous slurry is useful for chemical mechanical planarizing a semiconductor substrate. The slurry includes by weight percent, 0.1 to 25 oxidizing agent, 0.1 to 20 silica particles having an average particle size of less than 200 nm, 0.005 to 0.8 polyvinyl pyrrolidone for coating the silica particles, 0.01 to 10 inhibitor, 0.001 to 10 complexing agent and a balance water and incidental impurities; and the aqueous slurry having a pH of at least 7.

Abstract: Polishing pads having a surface morphology that results in a high degree of planarization efficiency when planarizing a wafer surface are disclosed. One conditioned polishing pad is non-porous and has a surface height distribution with a surface roughness Ra<3 microns. Another conditioned polishing pad is porous and has a surface height probability distribution with a pad surface height Ratio R?60%, or alternatively has an asymmetric surface height probability distribution characterized by an asymmetry factor A10?0.50. Methods of pad conditioning and planarizing a wafer using the polishing pads are also disclosed.

Abstract: A porous polishing pad is useful for polishing semiconductor substrates. The porous polishing pad has a porous matrix formed from a coagulated polyurethane and a non-fibrous polishing layer. The non-fibrous polishing layer has a polishing surface with a pore count of at least 500 pores per mm2 that decreases with removal of the polishing layer; and the polishing surface has a surface roughness Ra between 0.01 and 3 ?m.

Abstract: A method of polishing a surface (120) of an article, e.g., a semiconductor wafer (112, 212), using a polishing layer (108, 208) in the presence of a polishing medium, such as a slurry (116). The method includes selecting the rotational rate of the article or the velocity of the polishing layer, or both, so as to control either removal rate uniformity or the occurrence of defects on the polished surface, or both.

Abstract: A method of reducing defectivity during chemical mechanical planarization (CMP) in a system having a wafer membrane and a retaining ring is disclosed. The method includes planarizing test wafers using different values of ring pressure and wafer pressure to determine an optimum ring pressure and wafer pressure, i.e., the ring pressure and wafer pressure that results in a reduced defectivity.

Abstract: A polishing body, e.g., pad (200, 230, 260, 300) or belt (400, 500) having a polishing layer (214, 404) that includes a backmixing region (202, 232, 262, 308, 416, 508) wherein backmixing can occur within a slurry (116) between a wafer (204, 234, 264, 304, 408), or other article, and the polishing layer under certain conditions. The polishing layer includes a first groove configuration (206, 236, 266, 312, 428, 504) within the backmixing region and a second grove configuration (208, 238, 268, 320, 432, 520) outside of the backmixing region that is different from the first groove configuration. The first groove configuration is designed based upon whether or not the presence of spent slurry within the backmixing region is detrimental or beneficial to polishing the wafer.

Abstract: A polishing pad installation tool comprised of a base portion and at least one compressible layer in operative connection with the base portion. The compressible layer includes a plurality of apertures through an upper surface of the compressible layer. The tool further includes a plurality of parallel pins extending outwardly from the base portion through the apertures of the compressible layer. Each of the pins includes a collar portion in surrounding relation about each pin. When the compressible layer is in an uncompressed condition, the collar portions are beneath the upper surface of the compressible layer. The pins are positioned on the base portion in a pattern which corresponds to the holes in the polishing platen. The pins have diameters which are smaller than the diameters of the holes in a polishing pad. The collars have diameters larger than the diameters of the holes in the polishing pad.

Abstract: The method forms a transparent polishing pad by first step forming a plurality of openings through a disk-shaped pad body. The plurality of openings is distributed about the disk-shaped pad body and a transparent window within a portion of the pad body and the transparent window. Then sealing the openings in the transparent window with a transparent material allows transport of polishing fluids through the openings in the disk-shaped pad body and prevents transport of the polishing fluids through the transparent window.

Abstract: A polishing pad useful for chemical mechanical planarization has a polishing layer for planarizing substrates. The polishing layer comprises a radius that extends from a center of the polishing layer to an outer perimeter of the polishing layer; one or more continuous grooves formed in the polishing layer and extending inward from the outer perimeter of the polishing layer; and a circumference fraction grooved (CF). The CF occurs in the area extending from the outer perimeter of the polishing layer a majority distance to the center of the polishing layer; and CF is that portion of circumference at a given radius lying across the one or more continuous grooves divided by full circumference at the given radius. The CF remains within 25% of its average value as a function of the polishing layer radius.

Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness and hydrolytic stability.

Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing, pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad also exhibits a stable morphology that can be reproduced easily and consistently. The pad surface has macro-texture that includes perforations as well as surface groove designs The surface groove designs have specific relationships between groove depth and overall pad thickness and groove.area and land area.

Abstract: A method of fabricating a polishing pad in which a pad material includes a polishing layer overlying a substantially optically transparent backing layer is subjected to a process in which an optical window is formed in the pad material by removing a portion of the polishing layer and exposing an underlying portion of the substantially optically transparent backing layer. Prior to forming the optical window, the polishing layer is bonded to the backing layer to form a sealed interface, then a portion of the polishing layer is mechanically cut away from the backing layers. Since the backing layer is not pierced during the removal process, a liquid, such as an aqueous polishing slurry, cannot leak through the optical window and on to underlying portions of a polishing apparatus to which the pad material is mounted.

Abstract: A composition is provided in the present invention for polishing a composite semiconductor structure containing a metal layer (such as tungsten, aluminum, or copper), a barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride), and an insulating layer (such as SiO2). The composition comprises an aqueous medium, an oxidant, an organic polymer that attenuates removal of the oxide film. The composition may optionally comprise a complexing agent and/or a dispersant.

Abstract: A method for chemical mechanical planarization of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer using a two-step polishing process is provided. In the first step, the conducting metal overburden is substantially removed with little removal of the barrier or liner layer or the underlying dielectric structure. In the second step, the barrier layer is removed with little removal of the underlying dielectric layer. Five different methods and associated slurry compositions are described for the second polishing step, each adjusted to the state of the wafer following the first step of polishing. By using the appropriate method, the integrity of the remaining semiconductor structure can be substantially retained.