Abstract: The present invention discloses a method for providing full-duplex audio communication utilizing a half-duplex audio circuit in an audio communication system. The method comprises the steps of: (1) configuring an idle state, a listen state, and a talk state; (2) receiving an event triggered by one of an incoming speech, an outgoing speech, and a talk request from the half-duplex audio circuit; and (3) transitioning from one of the states to any one of the states in response to the event to provide full duplex communication.

Abstract: A bandgap voltage reference circuit and related method characterized in having a first current source for generating a first current having a positive temperature coefficient, a second current source for generating a second current having a negative temperature coefficient, and a resistive element to receive both the first and second current to develop a reference voltage. By configuring the circuit such that the magnitudes of the positive and negative temperature coefficients are substantially the same, the reference voltage becomes substantially invariant with changes in temperature. Another circuit is provided in conjunction with the voltage reference circuit to substantially equalize the drain-to-source voltage of the transistors used in the voltage reference circuit.

Abstract: There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.

Abstract: Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Abstract: A system and method is provided for using a linearized data structure to display a set of ordered images. The images are ordered based on the attributes of the images. The system and method includes displaying a target image and related images on a graphical user interface, where the related images are near the target image in the linearized data structure. The relative sizes of the target image and the related images may reflect the similarity of the related images to the attributes of the target image.

Abstract: In order to detect performance parameter variations at different locations, local parameter detectors are located at the various local locations. One of the local locations is selected as the reference location while the other local locations are selected as destination locations. The reference location is utilized to determine a reference parameter value, while each destination location compares its local parameter value to the reference parameter value. The parameter values are current encoded and the reference parameter value is sent to the other locations for the comparisons. The comparison at the destination locations each generates a corrective signal to compensate for the difference in the parameter value between the locations. Parameter compensation is provided to reduce performance skew among the distributed locations.

Abstract: A method and apparatus for efficient translation lookaside buffer (“TLB”) management of three-dimensional surfaces is disclosed. A three-dimensional surface is represented as a square pixel surface. The square-surface representation is stored in a single entry of the TLB.

Abstract: A processor comprises an instruction cache that stores a cache line of instructions and an execution engine for executing the instructions, along with a buffer to store a plurality of entries. A first logic circuit divides the cache line into instruction bundles, each of which gets written into an entry of the buffer. A second logic circuit reads out a number of consecutive instruction bundles from the buffer for dispersal to the execution engine to optimize speculative fetching and maximizing instruction supply to the execution resources of the processor.

Abstract: The invention provides a structure, method and means for receiving a reference frequency and a variable frequency, differentiating the frequencies, and generating a logic pulse in response to a first frequency leading a second frequency, the frequencies having a small phase difference. In an aspect, the invention maintains a signal when the reference frequency and the variable frequency transition. In another aspect, the invention provides additional timing balance to prevent early generation of the logic pulses. In another aspect, the logic pulses drive a charge pump used in one of a phase-locked loop and a delay-locked loop.

Abstract: An apparatus comprises a first device having one or more conductive areas to form a portion of an electromagnetic coupler and a socket to mount the first device relative to a second device having one or more conductive areas to form the electromagnetic coupler.

Abstract: The present invention is a method and apparatus for switching first and second tasks in an operating system. The first and second tasks each have first and second traditional states and first and second extended states, in a processing unit. The method comprises: (a) saving the first traditional and extended states from the processing unit to a buffer; (b) updating the buffer by replacing the first extended state by the second extended state; and (c) restoring the first traditional state and the second extended state in the processing unit from the updated buffer.

Abstract: A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers are daisy chained together with each register associated with a cache line. The first daisy chain defines a fill order of cache lines and the second daisy chain defines a lock order for the cache lines.

Abstract: An electronic assembly is provided having a die, a heat spreader, and a solidified solder material. A die includes a die substrate and an integrated circuit on a bottom surface of the die substrate. The heat spreader is located above the die and has left and right inclined faces. The left inclined face tapers from a point near a center of the die to a point upward and to the left of the upper surface. The right inclined face tapers from a point near the center upward and to the right above the upper surface. A solidified solder material fills regions between the upper surface and the inclined faces of the lower surface.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: A CBR/VBR traffic scheduler includes multiple CBR/VBR shapers to shape traffic over a wide range of peak cell rates for multiple CBR and VBR connection. Each shaper points to one or more VCs in a link list and includes a PCR counter initialized to a first value, an SCR counter initialized to a second and an arbitration counter. Each shaper is also connected to one of several clock sources, each having an associated clock cycle. A priority encoder, coupled to each arbitration counter, provides for determining priority between shapers having one or more associated VCs ready for transmission. Both the PCR counter and the SCR counter for each shaper is decremented during each associated clock cycle. For each shaper, when the PCR counter is decremented to a value of zero, the arbitration counter is initialized to a preset value and enabled for selection by the priority encoder.

Abstract: A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits of a result, moving a second operand occupying higher order bits of a second storage area to lower order bits of the result, and negating one of the first and second operands of the result.

Abstract: A method and apparatus comprising thinning a substrate sufficiently to allow it to be mechanically compliant with a material deposited on its surface is disclosed. The mechanical compliance allows a reduction in the interlayer stress generated by dissimilarities in the materials.

Abstract: The invention provides a system and method which can be used for pre-decoding one-byte instruction prefixes and branch instruction indicators. A static line detect generates a number of instruction indicators. Further, a prefix and branch decode unit combines at least two of the number of instruction indicators, and a pre-decode unit decodes the combined instruction indicators. Embodiments of the invention decode one byte prefixes without additional cycle penalty and generate one and two byte branch indications early.

Abstract: A first control hub component, within a computer system, having a first logic to synchronize an internal clock generator of the first control hub with an external clock generator in response to the external clock generator transitioning to a high power state. In response to the internal clock generator being synchronized with the external clock generator, the first logic initiates the first control hub to transmit a request packet to a second control hub via an interface. The first logic monitors the interface for receipt of a completion packet in reply to the request packet, wherein in response to the completion packet the first control hub is operable to continue communication with the second hub via the interface.

Abstract: A method includes transmitting packets on a bus and maintaining a number of the packets in-flight on the bus according to a number of active streams for the bus.