Abstract: A method and apparatus for storing information in a memory device that can be retrieved and displayed in a display device without “bootup” of the computer system.

Abstract: A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the bus is bounded, and establishing an isochronous interface between at least two devices, the isochronous interface supporting an X-T contract. A number of isochronous transactions and corresponding return transactions delivered across the bus is measured during a specified time interval.

Abstract: An optical switch having regions to which conductors are coupled outside an optical path of the optical switch. In one embodiment, the disclosed optical switch includes a plurality of first polarity regions arranged along an optical waveguide disposed in a semiconductor substrate layer. A first polarity region signal line conductor is in contact with each one of the plurality of first polarity regions outside an optical path of the optical waveguide. A plurality of second polarity regions are arranged along the optical waveguide disposed in the semiconductor substrate layer. A second polarity region signal line conductor is in contact with each one of the plurality of second polarity regions outside the optical path of the optical waveguide.

Abstract: An optical modulator that modulates light through the back side of a flip chip packaged integrated circuit die. In one embodiment, an optical modulator includes a p-n junction having a side wall that is substantially vertical or perpendicular relative to a surface of the integrated circuit die. A charged region is generated at the p-n junction and is modulated in response to an electrical signal of the integrated circuit die. An optical beam is directed through the back side, of the semiconductor substrate and through the charged region along the side wall p-n junction. The optical beam is deflected off a deflector back through the charged region along the side wall back out the back side. In one embodiment, the side wall p-n junction is provided with a metal oxide semiconductor (MOS) gate structure. In another embodiment, the side wall p-n junction is provided by an n− (or p−) well in a p− (or n−) epitaxy layer of the semiconductor substrate.

Abstract: A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.

Abstract: Various embodiments of a method for providing forward body bias (FBB) are disclosed. A first diode element is forward biased to a first voltage. A voltage proportional to the first diode voltage is converted into a current. A current is mirrored through a second diode element to generate a second diode voltage. A constant FBB based upon the second diode voltage is generated and applied to the bulk terminal of a field effect transistor (FET) of an integrated circuit die.

Abstract: The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop).

Abstract: An apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

Abstract: A method and apparatus of rendering an image is disclosed. In one embodiment, a graphic system has a switch detector, which detects a switch condition in the graphics system. The graphics system also has a rendering block, which renders a plurality of layers according to the detected switch condition.

Abstract: According to the invention, an electromagnetic radiation shielding cap is located over an electronic cartridge substrate. The electromagnetic radiation shielding cap includes an electromagnetic radiation shielding plate and an electromagnetic radiation shielding rim extending around a periphery of the electronic cartridge substrate. An edge of the electromagnetic radiation shielding rim contacts a thermally and electrically conductive heat plate located on an opposing side of the electronic cartridge substrate. The heat plate and the electromagnetic radiation shielding cap jointly define an electromagnetic radiation shielding enclosure around the electronic cartridge substrate.

Abstract: An integrated circuit (IC) package process is provided that includes forming a first via hole in a first substrate. Patterning signal lines on a first surface and a second surface of the first substrate. Attaching a second substrate to the first surface of the first substrate. Electronically connecting a portion of the signal lines of the first substrate and the second substrate. Attaching an electrical element to the first surface of the first substrate. Forming a via hole in a third substrate. Introducing conductive material over a first surface and a second surface of the third substrate. Forming a second circuit pattern on the first surface and the second surface of the third substrate. Additionally, attaching the third substrate to the first substrate with a second layer of adhesive. In an alternative embodiment, a process includes forming a via hole in a first substrate.

Abstract: The present invention comprises a phase-shifting mask and a process for fabricating such a phase-shifting mask. The phase-shifting mask has trenches with vertical sidewall profiles which are retrograde. The retrograde profiles balance the transmission and phase of the light transmitted through the phase-shifted openings relative to the non-phase-shifted openings. The retrograde profile may be formed from an isotropic plasma etch.

Abstract: A system is provided to obtain loss optimized output optical power by way of feedback control and stabilization in an optical signal switching or routing system. The optical signal switching or routing system includes at least two input optical fibers and at least two output optical fibers, a controllable mechanism for directing an optical beam from one of the input optical fibers to one of the output optical fibers, and a mechanism for measuring the optical power applied to output optical fiber. The measuring mechanism provides a measure of the output optical power through a signal processing apparatus to a control apparatus. Possible other inputs to the signal processing apparatus include the input optical power, test optical power, etc. The inputs to the signal processing apparatus are compared and the signal processing apparatus outputs a signal to the control apparatus to provide optimized output power.

Abstract: The invention relates to a hollow microbeam that is fabricated upon a base or pedestal. Processing of the hollow microbeam includes forming at least one hollow channel in the microbeam by removing temporary fillers after formation of the microbeam. The inventive microbeam may provide at least an order of magnitude increase in oscillational frequency over a solid microbeam.

Abstract: An integrated circuit package. The package includes a substrate that has a first internal conductive bus and a second internal conductive bus that are located on a common layer of the substrate and dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface of the package by vias that extend through the substrate. The first and second busses are located on a common layer of the substrate. The package contains an integrated circuit which is mounted to a heat slug that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers are connected to the internal busses by conductive strips that wrap around the edges of the shelf. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package.

Abstract: A hash CAM is provided with a hashing unit and a memory array. The hashing unit is designed to generate an n-bit index in response to an m-bit input, where n and m are positive integers, and n is smaller than m. The memory array is designed to store a number of truncated comparands of size r (in units of bits), and to output a selected one of the stored truncated comparands in accordance with the n-bit index, for comparison with a subset of r selected bits of the m-bit input, where r is also a positive integer, and m−r is less than or equal to n. In each of a number of applications, a look-up engine is provided with the hash CAM. In one particular application, a forwarding section of a networking device is provided with such look-up engine.

Abstract: Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as intralayer and interlayer dielectrics in advanced integrated circuits such as those which incorporate highly porous materials in a Cu damascene interconnect technology. An integrated circuit, embodying such a mechanically reinforced dielectric layer generally includes a substrate having interconnected electrical elements therein, a copper-diffusion barrier or etch stop layer disposed over the substrate, the copper-diffusion barrier or etch stop layer being patterned so as to provide a plurality of electrically insulating structures, and a low-k dielectric layer disposed around the plurality of structures.

Abstract: A device for confining an optical beam in an optical switch. In one embodiment, the disclosed optical switch includes an optical switching device disposed between an optical input port and an optical output port in a semiconductor substrate layer of an integrated circuit die. The semiconductor substrate layer is disposed between a plurality of optical confinement layers such that an optical beam is confined to remain within the semiconductor substrate layer until exiting through the optical output port. In one embodiment, a plurality of semiconductor substrate layers are included in the optical switch. Each of the semiconductor substrate layers is disposed between optical confinement layers such that optical beams passing through the semiconductor substrate layers are confined to remain within the semiconductor substrate layers until exiting through respective optical output ports. In one embodiment, at least one optical switching device is disposed in each of the plurality of semiconductor substrate layers.

Abstract: In one embodiment, a method comprises splitting a first data line into two or more first data line segments, wherein each of the first data line segments is connected to one transfer gate of a plurality of first data line transfer gates and to a first group of one or more sense amplifiers of a plurality of sense amplifiers; splitting a second data line into two or more second data line segments, wherein each of the second data line segments is connected to one transfer gate of a plurality of second data line transfer gates and to a second group of one or more sense amplifiers of the plurality of sense amplifiers; and providing voltage differences between each of the sense amplifiers of the first and second groups, wherein at least one of the voltage differences is an incorrect voltage difference that is corrected by the other voltage differences.

Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.