Abstract: A substrate which has a first conductive layer that is attached to a first dielectric layer. A second conductive layer is attached to the first dielectric layer. The second conductive layer may be a plated copper material that extends through a via opening of the dielectric and is attached to the first conductive layer. A third conductive layer is attached to the second conductive layer, including a sidewall of the third layer. A second dielectric can be attached to the third conductive layer. The third conductive layer may be a plated nickel-copper composition which improves the adhesion to subsequent layers in the substrate, particularly between the second dielectric and the sidewall of the second conductive layer.

Abstract: An apparatus for locking a printed circuit board inside a card cage is disclosed. For one embodiment of the locking assembly, the locking assembly is mounted on a printed circuit board. The locking assembly is movable from a unlocked position to a locked position to lock the printed circuit board into the card cage. The locking assembly is unmovable to return to the unlocked position without the aid of a separate unlocking mechanism.

Abstract: A method for manufacturing a semiconductor capacitor atop a conductive plug that is formed in a dielectric layer. A first oxide layer is formed on the dielectric layer and the conductive plug. Next, a crown opening in formed in the first oxide layer such that the conductive plug is exposed. Silicon sidewall spacers are formed on the sidewalls of the crown opening and then HSG silicon is formed on the silicon sidewall spacers. The HSG silicon and silicon sidewall spacers are oxidized and then a doped polysilicon layer is formed into the aid crown opening and over the oxidized HSG silicon. A thin dielectric layer is formed over the aid doped polysilicon layer and finally a top conductive layer is formed over the thin dielectric layer.

Abstract: A system and method to decode encoded video images in such a manner as to maintain high quality images while reducing the computation time needed to decode the images. The system takes into account that the resultant display generated may only have a fraction (1/4) of the resolution of the original image. Thus, optimizations are realized by modifying and combining the inverse discrete cosine transform (IDCT) and inverse weighting (IW) processes to process only the portion of the image to be displayed.

Abstract: A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

Abstract: An improved method and apparatus is used for storing and delivering information over the Internet and using Internet technologies. According to one embodiment of the present invention, a method and apparatus for maintaining statistics on a server is disclosed. According to an alternative embodiment, a method and apparatus is disclosed for predicting data that a client device may request from a server on a network. In another embodiment of the present invention, a method and apparatus is disclosed for managing bandwidth between a client device and a network. According to yet another embodiment, a method and apparatus is disclosed for validating a collection of data. According to yet another embodiment, a method for providing notification to clients from servers is disclosed.

Abstract: A muting circuit is provided to mute an audio signal at an audio output. The muting circuit includes a switching device having an enable input and being adapted to be coupled between an audio output and ground, the switching device being on when the enable input is at a deenergized voltage level. A mute controller is coupled to receive a mute signal and provide a signal to the enable input of the switching device to bias the switching device on.

Abstract: A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally.

Abstract: The present invention relates to a system comprising a host processor, a video subsystem and a cryptographic device. The cryptographic device includes dedicated circuitry to cause information associated with a financial transaction to be internally configured for display on a monitor of the video subsystem without being processed by host processor.

Abstract: Measurement corrections transmitted from reference stations at known positions are transmitted to differential Global Position System receivers for use in computation of position information relative to the receiver. In one embodiment, circuitry included in the receiver detects errors in transmissions of measurement correction data streams from the closest reference station and replaces erroneous portions of the data streams with corresponding portions received from a second reference station. Alternately, a plurality of measurement correction data streams received from a plurality of reference stations are combined to produce a combined measurement correction used to correct the position information received from satellites.

Abstract: An apparatus and method for performing byte swapping using a direct memory access (DMA) controller is provided. In a computer system, a DMA controller for a peripheral component is coupled to system memory via a bus. The DMA controller receives a command pointer to initiate a memory access operation. The command pointer specifies the location of the first DMA command in a command list to be executed by the DMA controller. Each DMA command includes an address word giving the starting address and length word indicating the number of data words to be accessed in memory. Because the data stored in memory is double-word aligned, the two least significant bits of the length word are not needed to perform the memory access and are instead used to indicate any byte swapping that is to be performed on the data during the memory access. During a memory access, the DMA controller swaps the bytes in each double-word of data as specified by the two least significant bits of the length word.