Abstract: An asynchronous digital phase detector. The digital phase detector includes an asynchronous state machine which simulates an edge triggered J-K flip flop. Additionally, the digital phase detector includes a reset line. The asynchronous state machine is implemented with logic which provides for optimal phase detector sensitivity and minimal dead zone. The logic within the digital phase detector is implemented with pass-transistors. The channel widths of the pass-transistors are selectively widened or narrowed to further increase the sensitivity of the phase detector.

Abstract: A method of detecting defects within an integrated circuit. Iddq testing for defects within integrated circuits includes measuring the quiescent (Iddq) current conducted by power supply nodes of the integrated circuit which are connected to a power supply while controlling signal levels of a plurality of inputs to the integrated circuit. The method of this invention includes calculating an upper threshold Iddq value and a lower threshold Iddq value. The input nodes are driven to a predetermined combination of input voltages and a corresponding Iddq value is measured. It is determined whether the measured Iddq value is between the upper threshold Iddq value and the lower threshold Iddq value. Another embodiment of this invention includes the upper and lower threshold values being dependent on a measured mean value of Iddq for the integrated circuit.

Abstract: A programmable delay line. The programmable delay line includes a series of delay cells which are programmably connected in series. The programmable delay line includes a main delay chain and auxiliary delay chains. The main delay chain includes unit delay cells. The auxiliary delay chains include a unit delay cell, and a delay cell which has a delay that is between one and two time greater than the delay through a unit delay cell. The delay resolution of the programmable delay line is less than the delay of a unit delay cell. The programmable delay line further includes a reference oscillator and calibration circuitry. The reference oscillator includes a series of unit delay cells, and generates a reference signal having a period which is an integer multiple of the delay of a unit delay cell. Variations in the delay of a unit delay cell influence the period of the reference signal.

Abstract: An LMDS system including a base station, subscriber units and subscriber modems. Transmission frequencies between the base station and the subscriber units are specified by the Federal Frequency Commission. Signal frequencies between the subscriber units and the subscriber modems are specified by industry standards. The subscriber units couple and frequency translate modulated signals between the base stations and the subscriber modems. The frequency translation requires an intermediate transmit oscillator and a local oscillator. The intermediate transmit oscillator, however, can also be used to frequency translate a local oscillator signal within each subscriber unit down to a lower frequency which allows a low cost phase locked loop chip to be used to phase lock the local oscillator in each subscriber unit to a reference source. A pilot tone can be coupled onto modulated signals transmitted from the base station to the subscriber units.

Abstract: A disk drive servo system which provides a position error signal with an increased signal to noise ratio. Mixing waveforms are generated for mixing with dibit burst signals created when a transducer on a recording head of a disk drive magnetically couples to reference position dibits located on a magnetic surface of the disk drive. The mixing waveforms are formed from a finite integer number of sine waves which are coherent with the dibit burst signals. The mixed dibit burst signal are integrated and summed to create the position error signal. Customizing the mixing waveforms allows the signal to noise ratio of the position error signal to be maximized when a magneto-resistive transducer within the disk drive servo system has one of several non-ideal characteristics.

Abstract: A ball grid array to integrated circuit interconnection. The interconnection includes a ball grid array substrate having a first surface and a second surface. The first surface comprising a plurality of substrate interconnection conductive pads. A power supply via connects a power supply conductive pad of the first surface to a first conductive area on the second surface. A ground via connects a ground conductive pad of the first surface to a second conductive area on the second surface. A decoupling capacitor connected between the first conductive area and the second conductive area. The interconnection further comprises an integrated circuit comprising a plurality of integrated circuit conductive pads. A plurality of smaller solder balls interconnect at least one of the integrated circuit conductive pads to at least one of the substrate interconnection conductive pads. A circuit board substrate is electrically interconnected by larger solder balls to the ball grid array substrate.

Abstract: A system and method for providing a controlled impedance flex circuit includes providing an insulative flexible substrate having opposed first and second surfaces and having through holes extending from the first surface to the second surface. A pattern of conductive traces is formed on the first surface of the flexible substrate. A film of conductive adhesive is applied to the second surface and to the through holes. The through holes are aligned to contact ground traces in the pattern of conductive traces on the first surface. Thus, a ground plane is established for creating an environment for high frequency signal propagation. The conductive adhesive may be a b-stage epoxy or a thermoplastic material. In the preferred embodiment, a tape automated bonding frame is fabricated.

Abstract: An electrical interconnection between a flip chip and a substrate. The interconnection includes a substrate having conductive pads to which wire bumps are attached. Each wire bump includes an elastically deformable stub section attached to the ball section, and a pointed tip. The pointed tip pierces a soft conductive layer located on a conductive pads of a flip chip. The elastic deformation of the stub section provides for consistent electrical connections between the flip chip and the substrate when the flip chip and the substrate are non-planar. An adhesive is located between the flip chip and the substrate and encompasses the wire bumps.

Abstract: A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector couples selected configuration memory cells to programmable switch elements that determine the configuration and function of the logic within the FPGA. A time slice controller determines which of the configuration memory cells the time slice selector couples to the programmable switch elements. The configuration memory cells may be implemented with half SRAM cells and the time slice selector may be implemented with P-channel transistors.

Abstract: An interface between a telecommunication network and multiple types of repositories. The invention is an apparatus and method for interfacing a CMIP network through a computer system to a repository. The computer system operates a log agent which translates CMIP instructions received by the computer system from the CMIP network to a set of standardized functions. The log agent is the same for all types of repositories. Each type of repository has a unique log access library. The log access library translates the standardized functions of the log agent to a form that can be interpreted by an application specific interface of the repository. Each type of repository has a unique application specific interface. Selection of a plurality of logged events can be determined by the log agent or the log access library.

Abstract: A high speed analog to digital sampling system. The invention allows for decimation and optimal storage of samples from an interleaved analog to digital conversion system. The circuit architecture provides for switchable flip-flops at the outputs of a set of interleaved analog to digital converters. Decimation is accomplished by only activating a selection of the analog to digital converters within the set of interleaved analog to digital converters. The flip-flops associated with the inactive analog to digital converters are configured to form a shift register. The samples of the activated analog to digital converters are shifted into the shift register. When all the flip-flops of the shift register are full, the samples are written to memory of the system. The shift register configuration allows the samples to be stored so that the allocation of system memory is optimized and the number of system memory writes is reduced.

Abstract: A field programmable gate array (FPGA) memory system which allows the same array of memory to contain both configurable memory and user memory. The FPGA user logic can modify the information contained within the configurable memory and the user memory. The information stored within the configuration memory defines the logic within the user logic. Therefore, the user logic can modify sections of the logic within the user logic. The configuration memory and the user memory share resources such as address decoders, bitlines and sense amplifiers.

Abstract: The present invention is an apparatus and method for using the dual port feature of Fibre Channel to allow multiple computer hosts to simultaneously access a cluster of memory units that are Fibre Channel arbitrated. Typical multiple host access schemes require an expensive Fibre Channel switch and do not allow simultaneous accessing. The dual port feature of Fibre Channel devices provides for fault tolerance and redundancy, but can be used for the present invention.