Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

Abstract: The invention includes an apparatus and method for determining an optimal route based upon path quality of routes to an access node of a wireless mesh network. The method includes receiving routing packets at the access node through at least one wireless route. Each routing packet includes route information that identifies the wireless route of the routing packet. A success ratio of a number of successfully received routing packets versus a number of transmitted routing packets is determined over a period of time T1, for each wireless route. The wireless route having a greatest success ratio is first selected, as are other wireless routes that have success ratios within a predetermined amount of the greatest success ratio.

Abstract: The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select lines are pre-charged. A self-timed charging circuit is initiated to provide an adequate amount of time to charge a selected row, and to initiate elimination of static current flowing to unselected rows after a self-timed delay. The other of the row select lines or the column select lines are then pre-charged. Memory cells are selected based upon the column address and the row address. One of two states of the memory cells can be based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

Abstract: The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for writing to the magnetic memory cell, determining a maximal magnitude of write current for writing to the magnetic memory cell, and calculating the selected magnitude of magnetic memory cell write current based on the minimal magnitude of write current and the maximal magnitude of write current.

Abstract: A method of forming a shared global word line MRAM structure is disclosed. The method includes, etching a trench in an oxide layer formed over a substrate, depositing an first liner material, anisotropically etching the deposited first liner material leaving the first liner material on edges of the trench and physically contacting a bottom of the trench, depositing an magnetic metal liner material, anisotropically etching the deposited magnetic metal liner material leaving the magnetic metal liner material over the first liner material on edges of the trench, so that the magnetic metal liner extends to and physically contacts the bottom of the trench, depositing a conductive layer;, and chemically, mechanically polishing the conductive layer.

Abstract: The invention includes a magnetic memory cell. The magnetic memory cell includes a reference layer having a preset magnetization. A barrier layer is formed adjacent to the reference layer. A sense layer is formed adjacent to the barrier layer. A first conductive write line is electrically connected to the reference layer. The magnetic memory cell further includes a second conductive write line having a gap, the gap being filled by at least a portion of the sense layer. A write current conducting through the second conductive write line is at least partially conducted through the portion of the sense layer, the write current increasing a temperature of the sense layer.

Abstract: The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The second layer includes a second plurality of magnetic tunnel junctions. The stacked magnetic memory structure further includes a common first group conductor connected to each of the first plurality of magnetic tunnel junctions and the second plurality of magnetic tunnel junctions.

Abstract: The invention includes an apparatus and a method for minimizing power supply sensitivity of a differential amplifier. The apparatus includes a current source providing a differential amplifier bias current to a common source node of the differential amplifier. A voltage sensor senses variations of a power supply associated with the current source. Variations sensed by the voltage sensor control a magnitude of the differential amplifier bias current. The method includes a current source providing the source current. A voltage potential of the common source node is sensed. The current source is adjusted depending upon the sensed voltage potential of the common source node, thereby adjusting a magnitude of the source current.

Abstract: The invention includes an apparatus and method for regulating a magnetic memory cell write current. The method includes modifying a magnetic memory cell write current by summing a write current offset to the magnetic memory cell write current, and determining whether writing to a magnetic memory cell with the modified magnetic memory cell write current results in a write error condition. If a write error condition exists, then the method includes incrementing the magnetic memory cell write current, or decrementing the magnetic memory cell write current, until the write error condition is eliminated.

Abstract: The invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic gate further includes a plurality of inputs. The plurality of inputs are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of inputs is a first voltage potential. The invention also includes an address decoder. The address decoder includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. An address decoder output is a function of charge on the charge holding device. The address decoder further includes a plurality of address lines.

Abstract: The invention includes an adjustable offset differential amplifier. The adjustable offset differential amplifier includes a first differential transistor receiving a first differential input, and a second differential transistor receiving a second differential input. A differential amplifier output includes an amplitude proportional to a difference between the first differential input and the second differential input. The first differential transistor includes a plurality of sub first differential transistors. Each sub first differential transistor includes an adjustable back gate bias. Control circuitry can be connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

Abstract: The invention includes a memory cell sensing system. The memory cell sensing system includes a plurality of memory cells located on a first plane of an integrated circuit. The system further includes a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane. Each sense amplifier is connectable to at least one memory cell based upon a relative location of each sense amplifier with respect to locations of the at least one memory cell. The invention also includes a method of sensing a state of a selected memory cell within a plurality of memory cells. A plurality of the memory cells are located on a first plane of an integrated circuit. A plurality of sense amplifiers are located on a sense plane that is adjacent to the first plane. The method includes connecting a sense amplifier to at least one memory cell based upon a relative location of each sense amplifier with respect to locations of the at least one memory cell.

Abstract: The invention includes an apparatus and method for generating a write current for a magnetic memory cell. The apparatus includes a write current generator for generating a write current, the write current being magnetically coupled to the magnetic memory cell. The apparatus further includes at least one test magnetic memory cell, the write current being magnetically coupled to the at least one test magnetic memory cell. A switching response of the at least one test magnetic memory cell determines a magnitude of the write current generated by the write current generator. The method for determining a write current for a magnetic memory cell includes supplying a test write current to a test magnetic memory cell, sensing a magnetic state of the test magnetic memory cell to determine a switching response of the test magnetic memory cell, and generating the write current having a magnitude that is dependent upon the switching response.

Abstract: The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.

Abstract: The invention includes a method of providing magnetic stability of a memory cell. The memory cell is generally located proximate to a conductive line, and proximate to a write mechanism that can set a magnetic state of the memory cell. The method includes receiving a representation of a maximum magnetic field intensity available from the write mechanism. A desirable placement of the memory cell relative to the conductive line can be generated for providing stability of the memory cell, while still allowing the write mechanism to change the magnetic state of the memory cell.

Abstract: A memory cell sensor including an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.

Abstract: The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells.

Abstract: The invention includes an apparatus and a method that provides a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell. The first memory cell and the second memory cell can be MRAM devices.

Abstract: The present invention provides a diversity transmission system. The diversity transmission system includes a diversity transmitter receiving incoming symbols. The diversity transmitter includes at least one transmitter antenna transmitting a plurality of multi-carrier modulated signals. Each multi-carrier-modulated signal includes a corresponding processed symbol sub-block stream. Each symbol of the processed symbol sub-block stream is based on a linear transform of a plurality of incoming symbols. The diversity transmission system further includes a diversity receiver. The diversity receiver includes at least one receiver antenna receiving the plurality of multi-carrier modulated signals after the multi-carrier modulated signals having been modified by transmission channels between the transmitter antennas and the receiver antenna.

Abstract: The invention includes an apparatus and method for scheduling wireless transmission of data blocks between at least one antenna of a base transceiver station and multiple subscriber units. The scheduling can be based on the quality of a transmission link between the base station antennas and the subscriber units, the amount of data requested by the subscriber units, and/or the type of data requested by the subscriber units. The scheduling generally includes assigning frequency blocks and time slots to each of the subscriber units for receiving or transmitting data blocks. The invention includes a method for transmitting data streams between a base transceiver station and a plurality of subscribers.