Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A photonic switch for an optical communication network includes a matrix of actuator-mirror assemblies and a corresponding matrix of optical ports. A first one of the actuator-mirror assemblies directs a beam of light received from an input optical port to a reference mirror, where it is reflected to a second actuator-mirror assembly that redirects the beam to an output optical port. Each of the actuator-mirror assemblies includes a mirror-coil assembly mounted to a gimbal, with stationary magnets being positioned adjacent a corresponding one of the coils such that when current flows through the coils a force is generated that causes the mirror-coil assembly to tilt. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: The present invention provides a spin-valve magnetoresistance sensor in which are formed, on top of the substrate, free layers, and pinned layers, enclosing a nonmagnetic spacer layer, and an antiferromagnetic layer adjacent to the pinned layers. The sensor is also equipped with a back layer including at least two nonmagnetic metal layers adjacent to the free layers on the side of the free layers opposite the nonmagnetic spacer layer. The back layer has at least one nonmagnetic metal layer of Cu with high electrical conductivity, preferably formed adjacent to the free layers, as for example in a two-layer structure of Cu and Ru or a three-layer structure Ru/Cu/Ru. In addition to a high read output, fluctuations in Hint with the film thickness of the back layer can be suppressed and sensor characteristics stabilized, and high recording densities can be realized.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A method for maximizing light transmission through an optical switch which includes a first mirror to direct a beam of light received from an input optical port to a second mirror that redirects the beam of light to an output optical port, the first and second mirrors each being pivotally actuated in first and second directions. The input and output mirrors are simultaneously moved through a sequence of coordinate positions about an origin, the input and output mirrors moving in both the first and second directions, with a light intensity value being read at each coordinate position to find a maximum light intensity value. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A spin-valve magnetic transducing element. In one embodiment, a spin-valve magnetic transducing element is disclosed in which a ferromagnetic tunneling junction film, including first and second ferromagnetic layers and an insulating layer is enclosed between the ferromagnetic layers. A nonmagnetic metal thin film is inserted between the second ferromagnetic layer and the insulating layer, all of which are formed on a substrate.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises a first buried layer disposed in a first epitaxial layer formed on a substrate, a second buried layer disposed in a second epitaxial layer formed on the first epitaxial layer, with the first and second buried layers being spaced vertically apart in a substantially parallel configuration such that a JFET conduction channel of the first conductivity type is formed between the first and second buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the drain region of the offline transistor.

Abstract: Method of fabricating a lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Abstract: A method of manufacturing a thin film magnetic head includes forming a recording gap layer of a non-alumina base nonmagnetic material on a lower magnetic pole layer, the lower magnetic pole layer being composed of materials that are milled at the same rate. An upper magnetic pole layer is formed on the recording gap layer, and a single piece of equipment is used to trim the lower magnetic pole layer and pattern the recording magnetic gap layer such that the lower magnetic pole layer has a width that is substantially the same as that of the upper magnetic pole layer. The recording gap layer and the upper and lower half-gap layers are then removed over a region of the underlying substrate. Prescribed areas of tan air-bearing surface (ABS) are then etched to form a slider shape having a protruding part and a depressed part, the ABS and the side surface having a common edge such that the depressed part along the common edge extends into, but not beyond, the region.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: An actuator for tilting a moveable object such as a mirror includes a base and a coil-object assembly that includes first and second pairs of coils each of which is attached to the object, the first pair of coils being arranged along a longitudinal axis, and the second pair of coils being arranged along a transverse axis substantially orthogonal to the longitudinal axis. A gimbal has an attachment section attached to the object, and mounting sections connected via a plurality of beams to the attachment section, the mounting sections being attached to the base. A permanent magnet is positioned adjacent a corresponding one of each of the coils such that when current flows through the coils a rotational force is generated that causes the coil-object assembly to rotate about an axis. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A power integrated circuit includes a gate driver coupled to an output transistor having a plurality of segments. The gate driver also has a plurality of segments, each of the segments of the driver circuit being located adjacent a corresponding one of the segments of the output transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).