Patents Represented by Attorney Burgess & Bereznak, LLP
  • Patent number: 6489190
    Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: December 3, 2002
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 6477019
    Abstract: Prevention of the formation of unwanted profiles in the ABS surface by etching of the slider ABS surface, even when gap layers are formed from non-alumina-base nonmagnetic materials differing from the component material of the substrate. Numerous thin film magnetic head elements, consisting of multiple layers including magnetic gap layers composed of nonmagnetic materials, are formed in a lattice array on the surface of a wafer. In the process of formation of these elements, the component materials of the magnetic gap layers existing in the region to be etched in order to form the slider shape are removed in advance. The wafer on the surface of which the elements are formed is cut into individual head blocks, and the surfaces opposing the magnetic recording media, consisting of a cut surface of said head block, are formed into a slider shape by etching.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: November 5, 2002
    Assignee: Read-Rite SMI Corporation
    Inventors: Naoto Matono, Tatsuya Shiromoto, Tomihito Miyazaki
  • Patent number: 6468847
    Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: October 22, 2002
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 6465291
    Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: October 15, 2002
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 6461385
    Abstract: Bone augmentation in a mammalian body to enhance the mechanical strength of a prosthesis is provided by reinforcement of bone in the region surrounding the implant device. A number of fibrillar wires are formed on the prosthetic implant device. Formation of the fibrillar wires comprises gauging the implant device so that the fibrillar wires are formed by peeling them from the implant device. Alternatively, formation of the fibrillar wires may comprise forming a mesh of fibrillar wires having a woolly structure, forming the mesh around the prosthetic implant device, and attaching a number of the fibrillar wires to the prosthetic implant device. A coating is formed on the fibrillar wires and an associated prosthetic implant device. The coating comprises bone morphogenetic proteins along with osteoinductive factors and osteoconductive factors that function as nutrients, anti-microbial and anti-inflammatory agents, and blood-clotting factors.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: October 8, 2002
    Assignee: Comfort Biomedical Inc.
    Inventors: Gregory G. Gayer, Christopher J. Comfort
  • Patent number: 6451514
    Abstract: An apparatus and method for formation of the upper magnetic pole layer of a thin film magnetic head. The presently described method for formation of the upper magnetic pole layer of a thin film magnetic head enables the formation with submicron precision of a resist layer for use in forming the upper magnetic pole layer, which must necessarily be formed on a surface having a step, which can contribute to further improvement of areal recording densities. A frame for use in forming the upper magnetic pole layer is formed from multiple resist layers, and the relatively thick lower resist layer is formed by a vacuum thin film formation method.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: September 17, 2002
    Assignee: Read-Rite Corporation
    Inventor: Daisuke Iitsuka
  • Patent number: 6430009
    Abstract: A compound thin film magnetic head in which the upper shield of the readout MR head also serves as the lower magnetic film of the write inductive head. The upper shield has a layered structure including a shield part of soft magnetic material functioning as a shield to magnetically shield the MR head, a lower pole part and transition part of soft magnetic material functioning as a write magnetic pole opposing the upper pole of the inductive head, and a nonmagnetic separation layer to magnetically separate these. Between the lower pole part and the transition part, an additional nonmagnetic separation layer can be provided. The shield part can be configured from multiple magnetic films formed in layers and enclosing a nonmagnetic separation layer.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: August 6, 2002
    Assignee: Read-Rite SMI Corporation
    Inventors: Kenji Komaki, Naoto Matono, Ryuichiro Yoshizaki, Hirohiko Kamimura
  • Patent number: 6424007
    Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: July 23, 2002
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney