Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming parallel arranged drift regions, each of which is interleaved with an insulating layer and a conducting layer that functions as a field plate. Source and body regions of opposite conductivity types are formed, with the body regions separating the source regions from the drift regions. An insulated gate is formed adjacent the body region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure, It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: An inverse type compound thin film magnetic with good dispersion of the heat generated in the magnetoresistance (MR) element, ensuring thermal reliability. In one embodiment, an electromagnetic induction type thin film magnetic head, a magnetoresistance effect type thin film magnetic head, a first protective film, a heat dispersion layer with thermal conductivity higher than the first protective film, and a second protective film are formed in succession on a substrate.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer Is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer.

Abstract: A spin-valve magnetic resistance sensor. In one embodiment, the spin-valve magnetic resistance sensor includes a pair of ferromagnetic layers with a non-magnetic layer sandwiched in between. The pair of ferromagnetic layers, the non-magnetic layer and an antiferromagnetic layer are laminated on a substrate. The antiferromagnetic layer is formed using an antiferromagnetic material which uses a Pt—Mn—X alloy, Ir—Mn—X alloy, Rh—Mn—X alloy, Ru—Mn—X alloy or Pd—Mn—X alloy. X indicates one or more elements selected from a set consisting of elements of groups IIA, IVA, VA, IIIB and IVB of the periodic table. X is in the range of 0.1 at % to 15 at %.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A magnetic head manufacturing method. In one embodiment, a wafer including magnetic head devices formed on the surface thereof are cut out into individual sliders. Photoresist is applied on the air bearing surfaces of the sliders and is then baked. The surface tension causes the photoresist at the peripheral regions of the air bearing surface to taper and become rounded or thinned. The air bearing surface is then uniformly dry-etched such that the peripheral regions of the air bearing surface are rounded in a tapered shape.

Abstract: A MOSFET that provides high current conduction at high frequency includes a deposited layer over a substrate of a first conductivity type, with source and drain regions adjoining a top surface of the epitaxial layer. The drain region has a first portion that extends vertically through the epitaxial layer to connect to the substrate and a second portion that extends laterally along the top surface. A first region is disposed in the epitaxial layer between the extended region and the source region. An insulated gate is located above the first region between the source region and the second portion of the drain region. A drain metal layer contacts a bottom surface of the substrate, and a source metal layer that substantially covers the top surface connect to the source region.

Abstract: A magnetic transducing element in which a ferromagnetic tunneling junction film, including first and second ferromagnetic layers and an insulating layer are enclosed between the ferromagnetic layers, and a nonmagnetic metal thin film is inserted between the second ferromagnetic layer and the insulating layer, is formed on a substrate.

Abstract: A power integrated circuit includes a gate driver coupled to an output transistor having a plurality of segments. The gate driver also has a plurality of segments, each of the segments of the driver circuit being located adjacent a corresponding one of the segments of the output transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Abstract: A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate structure in which the insulated gate is coupled to the gate electrode through contacts at a plurality of locations. The source electrode includes first and second segments. The first segment is interposed between the drain electrode and the gate electrode and acts as a field plate.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the drain region of the offline transistor.

Abstract: A thin-film magnetic head in which has a spin-valve element and a pair of electrode layers that are electrically connected to both ends of the element in the direction of width. A tantalum film is laminated as a protective layer on the uppermost part of the abovementioned element. A pair of electrode layers are caused to overlap on both end portions of the element. The tantalum oxide present in the areas on which the electrode layers overlap is removed prior to the formation of the electrode layers so that the electrical resistance between the electrode layers and the element is reduced.

Abstract: A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.