Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: An apparatus is disclosed for thawing a frozen food item, including a chamber dimensioned to receive the frozen food item, a heat exchanger operable to either heat air in the chamber or to cool the air in the chamber, a fan for creating a flow of the air within the chamber; and a tray disposed in the chamber and having an upper surface adapted to receive and support a lower surface of the frozen food item. The tray is adapted to receive a portion of the flow of air and to provide the portion of the flow of air to the lower surface of the food item such that the portion of the flow of air is distributed across the lower surface of the food item and directed upwardly about the food item.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power tables are created based upon the macro's input switching factor percentage and the clock activation percentage. These power tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate energy tables are produced.

Abstract: A metal golf club head that allows a user to customize the location of the center of gravity. The metal golf club head comprises a hollow body with a weighting port. The weighting port allows a user to place weighting material inside the hollow body, customizing the location of the center of gravity, the swing weight, the total weight, and the balance of the golf club.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.

Abstract: The present invention provides for making a comparison between a first video frame and a second video frame to determine the extent of a fear reaction in a test animal. Frame comparison logic is configured to quantify any change of a value associated with at least one pixel between the first video frame and the second video frame. A centroid calculator is configured to determine the position of a centroid of a video frame. Brainwaves of a test animal are also simultaneously measured and recorded. A processor correlates, as a matter of time, the recorded brainwaves with the change of status of the pixilated image information as a function of time.

Abstract: A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same “front-end” pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit checks the GP instructions for dependencies and resolves these dependencies. At the dispatch point within the pipelines the Instruction Unit sends valid GP instructions to the GP Unit and SIMD instructions to an SIMD issue queue. In the SIMD issue queue the Instruction Unit checks the SIMD instructions for dependencies and resolves these dependencies. Then the SIMD issue queue dispatches the SIMD instructions to the SIMD Unit. Accordingly, dependencies involving SIMD instructions do not affect GP instructions because the SIMD dependencies are checked and resolved independently.

Abstract: An apparatus, a method, and a computer program are provided for the generation of constant incremental increases while changing core clock frequencies. In computer systems, oftentimes frequency changes are useful. Maintaining the clocking ability of the computer system, though, can be a difficult task. To maintain the time keeping ability, time base logic is utilized with the free-running clock, which can be frequency limited. However, a plurality of communication channels in conjunction with an adder system is employed to effectively adjust for an ever increasing frequency to allow for a effective timekeeping regardless of the core frequency.

Abstract: A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data items is configured in accordance with one of a plurality of access modes. Each of the plurality of directory information items comprises indicia of the access mode of its associated data item. A multiplexer couples to the memory and comprises a multiplex ratio. A plurality of buffers couple to the multiplexer and to the memory. The multiplex ratio is a function of the number of buffers in the plurality of buffers. A plurality of multiplexer/demultiplexers (MDMs) each uniquely couple to a different one of the plurality of buffers. A plurality of processing elements couple to the memory; each of the processing elements uniquely couples in a point-to-point connection to a different one of the plurality of MDMs.

Abstract: A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of the dI/dt circuit to indicate success or failure. When errors are detected, the circuit allows for erroneous codes to be replaced with accurate ones. Using this circuit, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment can be more easily achieved.

Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

Abstract: A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse width is larger than a maximum clock pulse width. Upon a determination that the clock pulse width is larger than a maximum clock pulse width, the clock pulse width of the clock signal is limited.

Abstract: A method and an apparatus are disclosed for providing the order of transmission of radio link packets of various flows by the outer DSCP markings contained in correlated IDPs. This is achieved by a BSC sorting the IDPs by their associated outer DSCP marking and placing the IDP into a BSC memory as a function of the outer DSCP marking, and then scheduling the IDPs on the basis of in which BSC memory they have been placed.

Abstract: The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.

Abstract: A minimally invasive method for stabilizing adjacent vertebrae to be fused is accomplished with a device configured to interlink the pedicles of the adjacent vertebrae and including multiple pedicle screws. Each of the pedicle screws has a screw head configured to receive a connecting rod in a position, in which the rod and the receiving pedicle screw are vertically aligned.

Abstract: Disclosed is a method of and apparatus for increasing the capacity of a wireless communication system. This is accomplished by having users that can support a higher than base modulation order be required to do so under predetermined conditions such as electrical distance from a base transceiver station (BTS) antenna to a user, the reception of data in a high speed burst (HSD) and the like. The same digital processor apparatus that may be used to provide a base order modulation scheme may be reprogrammed in a more complex fashion to provide signal processing at the higher modulation rate for any given user channel.

Abstract: Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load and/or store instruction specifying the same address. If such a previous load/store instruction is found, the thread information is used to determine if the previous load/store instruction is from the same thread. If the previous load/store instruction is from the same thread, the cache hit signal is ignored, and the load instruction is stored in the queue. A load/store unit is also described.

Abstract: The present invention is a portable, configurable, inexpensive large scale projection system. The system is comprised of a plurality of projectors mounted on a structure and a display screen. The structure can be reconfigured to hold more or fewer projectors, and can be disassembled for easy transportation and reassembled. In an embodiment, the structure is comprised of containers and the projectors are mounted on calibration tables.

Abstract: The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.