Abstract: The present invention provides for creating and employing code and data partitions in a heterogeneous environment. This is achieved by separating source code and data into at least two partitioned sections and at least one unpartitioned section. Generally, a partitioned section is targeted for execution on an independent memory device, such as an attached processor unit. Then, at least two overlay sections are generated from at least one partition section. The plurality of partition sections are pre-bound to each other. A root module is also created, associated with both the pre-bound plurality of partitions and the overlay sections. The root module is employable to exchange the at least two overlay sections between the first and second execution environments. The pre-bound plurality of partition sections are then bound to the at least one unpartitioned section. The binding produces an integrated executable.

Abstract: A closure member, such as a set screw, and complementary receiving member are included in a medical implant device. The receiving member has a plurality of noncontiguous, threaded walls substantially defining a bore for receiving the threaded closure member. When the closure member is inserted into the receiving member, their respective threads interlock to join the noncontiguous walls of the receiving member. The closure member has an outer thread configured to interlock with the inner walls of the receiving member in a manner that aids in preventing the noncontiguous walls of the receiving member from moving away from the closure member. In certain embodiments, the closure member's outer thread includes a trailing edge having a point that is rearward of the trailing edge's root, and the outer thread includes a leading edge having a point that is forward of the leading edge's root.

Abstract: The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping table, wherein the mapping table is read by the dynamic debugger.

Abstract: The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration information. An initialization module is coupled to the configuration module and a memory device and is configured to receive initialization control commands and associated configuration information from the configuration module, and to send memory initialization commands to the memory device based on received initialization control commands and associated configuration information.

Abstract: The present invention renders a triangular mesh for employment in graphical displays. The triangular mesh comprises triangle-shaped graphics primitives. The triangle-shaped graphics primitives represent a subdivided triangular shape. Each triangle-shaped graphics primitive shares defined vertices with adjoining triangle-shaped graphics primitives. These shared vertices are transmitted and employed for the rendering of the triangle-shaped graphics primitives.

Abstract: A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function GI, I+1=GI OR GI+1 AND PI is to be performed. When GI+1=CI+1, GI, I+1=CI, arrival times of generate signals GI and GI+1, are investigated. If GI arrives before GI+1, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function GI, I+1?=GI? AND GI+1? OR PI? is to be performed. If the generate signal GI? arrives before GI+1?, a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.

Abstract: A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.

Abstract: The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.

Abstract: In the present invention, global information is passed from a first execution environment to a second execution environment, wherein both the first and second processor units comprise separate memories. The global variable is transferred through the invocation of a memory flow controller by a stub function. The global descriptor has a plurality of field indicia that allow a binder to link separate object files bound to the first and second execution environments.

Abstract: Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.

Abstract: A unique tool for removing dents from sheet metal that is best accessed or can only be accessed from the same side of the metal surface from which the dent was originally created. The tool has a lower plate and an upper plate. The lower plate has a lower side proximate to a dent in a surface to be repaired and an upper side. The upper plate has a lower side proximate to the upper side of the lower plate and an upper side. The tool has a plurality of pins slidably extending through the lower and upper plates, the pins having heads proximate to said upper side of said upper plate and lower attachment ends adapted for receiving an adhesive. The tool further has a displacing member for selectively displacing the upper plate away from the lower plate so that the upper side of the upper plate will push the heads of the pins upwardly as the upper plate is displaced, causing the lower attachment ends to move upwardly.

Abstract: A method and system for allowing a user to interface to an interactive voice response system via natural language commands. The system plays a prompt that initiates user interaction. In certain embodiments, the system detects initial user speech, wherein the initial user speech begins during the prompt or during a silence after the prompt. Then, the system determines whether the user speech restarts (second user speech) within a predetermined time period, wherein the predetermined time period is dependent upon whether the initial user speech began during the prompt or during the silence. If the user speech does restart, then the system uses the second user speech for recognition purposes. If the user speech does not restart, then the system uses the initial user speech for recognition purposes.

Abstract: The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assume maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculate the actual interference between the signals.

Abstract: A golf club head that allows a user to customize the location of the center of gravity. The golf club head comprises a club head having a hollow cavity with a weighting port. The weighting port allows a user to place weighting material inside the hollow cavity, customizing the location of the center of gravity, the swing weight, the total weight, and the balance of the golf club.

Abstract: The present invention provides an integrated circuit. The integrated circuit has a plurality of chip areas. The integrated circuit also has a plurality of temperature sensors, at least one per chip area. The temperature sensors generate a voltage proportional to the measured temperature. A voltage comparator compares the voltage output of the plurality of temperature sensors. The voltage comparator is further employable to generate a signal if the difference between the voltages generated by the plurality of temperature sensors exceeds a threshold.

Abstract: The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.

Abstract: An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.

Abstract: The present invention provides a method, apparatus, and computer program for measuring the current leakage in a Low Pass Filter (LPF) capacitor of a Phased Locked Loop (PLL). As a result of thinner and thinner film capacitors in Complementary Metal-Oxide Semiconductor (CMOS) technology, leakage current, which causes a PLL to drift out of phase lock, has become an increasingly difficult problem. To overcome the leakage current problems, knowing the leakage current of an LPF capacitor is important to implement the correction circuitry. In the present invention, an external interface and a time interface analyzer are used to charge the LPF capacitor and measure the output frequency of the PLL's Voltage Controlled Oscillator. Because of the change in the output frequency, the leakage current can be determined.

Abstract: A method and apparatus for dynamically assigning a home agent to a mobile station for a mobile IP session. The method and apparatus allow the telecommunications network to assign the home agent that is best able to serve the mobile station. This is achieved by utilizing a predetermined IP address that indicates to the network components, such as the packet-switched data network, the home agent, the home authorization, authentication, and accounting server, and the like, that the mobile station is requesting a dynamically assigned home agent.