Patents Represented by Attorney Carr LLP

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  • High performance implementation of exponent adjustment in a floating point design
    Patent number: 7290023
    Abstract: A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh, Kevin D. Tran
  • System and method for examining high-frequency clock-masking signal patterns at full speed
    Patent number: 7289926
    Abstract: The present invention provides for a method for examining high-frequency clock-masking signal patterns at a reduced frequency. A first mode of a first shift register is selected. A plurality of bits is loaded on the first shift register at a first frequency. A second mode of the first shift register is selected. A first mode of a second shift register is selected. The plurality of bits is loaded on the second shift register. A second mode of the second shift register is selected. A first mode of a third shift register is selected. The plurality of bits is loaded on the third shift register. A second mode of the third shift register is selected and the plurality of bits is loaded from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Jieming Qi
  • Deep power saving by disabling clock distribution without separate clock distribution for power management logic
    Patent number: 7284138
    Abstract: An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Mack Wayne Riley, Daniel Lawrence Stasiak, Michael Fan Wang, Stephen Douglas Weitzel
  • Service-portal enabled automation control module (ACM)
    Patent number: 7266589
    Abstract: The invention presents a system and a method for assisting automation control module (ACM) customers to retrieve information relevant to their specific ACM(s). A service-portal ACM combines a conventional ACM with a service portal and/or a general-purpose computer to facilitate locating relevant information by the customers. The service-portal ACM comprises a first central processing unit (CPU), and a first memory operably connected to the first CPU. A second CPU is operably connected to the first CPU, and a second memory is operably connected to the second CPU for storing a service-portal database containing a first set of service-portal data and one or more links to a second set of service-portal data stored in a remote network server. A first network interface is operably connected to the second CPU and to a gateway configured for enabling the second CPU to communicate with the remote network server.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: September 4, 2007
    Assignee: General Electric Company
    Inventors: Carrie Brownhill, Bill Huntley, David Collier, Ferrell Mercer, Jason Kadingo, Brad Bolfing, Dan Miller
  • Method and apparatus for managing a plurality of mobile nodes in a network
    Patent number: 7257402
    Abstract: A method and apparatus for allowing a plurality of mobile nodes to access a network with one or more Network Access Identifiers (NAIs), This allows a user to access a network with multiple mobile nodes using a single NAI. The method and apparatus is achieved by the addition of a Session/Device Extension, a Host Identification Extension, a Host Identification NAI Extension, and/or a Lease Time Extension.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: August 14, 2007
    Assignee: Nortel Networks Limited
    Inventors: Mohamed Khalil, Haseeb Akhtar, Emad Qaddoura, Raja Narayanan
  • Ball grid array package construction with raised solder ball pads
    Patent number: 7253510
    Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventor: Paul Marlan Harvey
  • Beam steering array antenna method and apparatus
    Patent number: 7250908
    Abstract: Disclosed is an apparatus which reduces the number of phase shifters required in an antenna array. This is accomplished by supplying standing waves from the phase shifters to each of the radiating elements in a column or row. The standing waves in the rows are orthogonal to the standing waves in the columns. Each of the radiating elements combines the applied standing waves, the phases of which determine the angle of the resultant beam.
    Type: Grant
    Filed: May 15, 2004
    Date of Patent: July 31, 2007
    Assignee: Southern Methodist University
    Inventor: Choon Sae Lee
  • Dynamic system bus encryption using improved differential transitional encoding
    Patent number: 7248696
    Abstract: The present invention provides data encryption for a differential bus employing transitional coding. The present invention maps, encodes and encrypts input data as a logic status for a given bus transfer cycle. The mapping, encoding and encrypting of the input data changes from bus transfer cycle to bus transfer cycle. The mapping, encoding and encrypting is a function of a pseudo-random number. A logic status is differentially transmitted from a bus transmitter to a bus receiver, to be mapped, decrypted and decoded as the corresponding output data.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: July 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: David John Craft, Charles Ray Johns
  • Protecting one-hot logic against short-circuits during power-on
    Patent number: 7245159
    Abstract: A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: July 17, 2007
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Christian Jacobi, Hwa-Joon Oh, Silvia Melitta Mueller
  • Method and apparatus for creating and executing integrated executables in a heterogeneous architecture
    Patent number: 7243333
    Abstract: The present invention provides a compilation system for compiling and linking an integrated executable adapted to execute on a heterogeneous parallel processor architecture. The compiler and linker compile different segments of the source code for a first and second processor architecture, and generate appropriate stub functions directed at loading code and data to remote nodes so as to cause them to perform operations described by the transmitted code on the data. The compiler and linker generate stub objects to represent remote execution capability, and stub objects encapsulate the transfers necessary to execute code in such environment.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Kathryn M. O'Brien, John Kevin O'Brien, Valentina Salapura
  • Establishing command order in an out of order DMA command queue
    Patent number: 7243200
    Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Norman Day, Charles Ray Johns, Peichun Peter Liu, Thuong Truong, Takeshi Yamazaki
  • Method and apparatus for predicting fan failure
    Patent number: 7239968
    Abstract: A method and apparatus are provided for monitoring and adjusting angular speed or rotational frequency of a fan as well as wear. As a result of being able to monitor the angular speed or rotational frequency of a fan, a prediction of both wear and failure can be made. Due largely to increasing internal friction related to the amount of wear, the energy required to operate a fan at a given angular speed or rotational frequency varies. Hence, an algorithm and certain devices can be employed to make wear and failure predictions of either an mechanical or electrical fan based on energy consumption relative to an angular speed or rotational frequency.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: July 3, 2007
    Assignee: Valere Power, Inc.
    Inventors: Gregory H. Fasullo, Rick L. Barnett
  • Leakage current reduction system and method
    Patent number: 7237163
    Abstract: An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: June 26, 2007
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Hwa-Joon Oh, Silvia Melitta Mueller, Joel Silberman
  • Round robin selection logic improves area efficiency and circuit speed
    Patent number: 7231479
    Abstract: A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks of requestors and pointers operate on sequential AND-OR-Inverter/OR-AND-Inverter (AOI/OAI) logic to advance the pointer and efficiently select those requestors with pending requests. The use of the AOI/OAI logic circuitry in the banks of requestors and pointers allows for efficient selection and minimization of complex circuitry reducing the overall circuit area.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: June 12, 2007
    Assignee: International Business Machines Corporation
    Inventors: Glen Howard Handlogten, Peichun Peter Liu, Jieming Qi
  • Proxy direct memory access
    Patent number: 7225277
    Abstract: A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: May 29, 2007
    Assignee: International Business Machines Corporation
    Inventors: Charles Ray Johns, Peichun Peter Liu, Thuong Quang Truong, Asano Shigehiro, Takeshi Yamazaki
  • Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture
    Patent number: 7225431
    Abstract: The present invention provides inserting and deleting a breakpoint in a parallel processing system. A breakpoint is inserted in a module loaded into the execution environment of an attached processor unit. The breakpoint can be inserted directly. Furthermore, the unloaded image of the module can also have a breakpoint associated with it. The breakpoint can be inserted directly into the module image, or a breakpoint request can be generated, and the breakpoint is inserted when the module is loaded into the execution environment of the attached processor unit.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: May 29, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Kathryn M. O'Brien, John Kevin O'Brien, Valentina Salapura
  • Method and apparatus for measuring and adjusting the duty cycle of a high speed clock
    Patent number: 7225092
    Abstract: An apparatus, a method, and a computer program are provided to measure the duty cycle of a clocking signal in a processor. Traditionally, variations in the duty cycles of clocks within microprocessors have been of considerable concern. By employing frequency dividers and AND gates, the duty cycles of clocks can be precisely measured and adjusted accordingly to account for variation that might occur. The measurements and adjustments, therefore, can improve the operation of a microprocessor or any other clocked semiconductor.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: May 29, 2007
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Kazuhiko Miki
  • Breathing device utilizing a catalytic oxygen generation method
    Patent number: D549341
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 21, 2007
    Assignee: Oxysure Systems, Inc.
    Inventors: Julian T. Ross, Kraig Kooiman
  • Breathing device utilizing a catalytic oxygen generation method
    Patent number: D549342
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 21, 2007
    Assignee: Oxysure Systems, Inc.
    Inventors: Julian T. Ross, Kraig Kooiman
  • Housing for a drapery motor
    Patent number: D554586
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: November 6, 2007
    Inventor: Gerrit Jan Vrielink