Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.

Abstract: A non-uniform memory access (NUMA) data processing system includes a plurality of nodes coupled to a node interconnect. The plurality of nodes contain a plurality of processing units and at least one system memory having a table (e.g., a page table) resident therein. The table includes at least one entry for translating a group of non-physical addresses to physical addresses that individually specifies control information pertaining to the group of non-physical addresses for each of the plurality of nodes. The control information may include one or more data storage control fields, which may include a plurality of write through indicators that are each associated with a respective one of the plurality of nodes. When a write through indicator is set, processing units in the associated node write modified data back to system memory in a home node rather than caching the data.

Abstract: A method for improving performance of a multiprocessor data processing system having processor groups with shared caches. When a processor within a processor group that shares a cache snoops a modification to a shared cache line in a cache of another processor that is not within the processor group, the coherency state of the shared cache line within the first cache is set to a first coherency state that indicates that the cache line has been modified by a processor not within the processor group and that the cache line has not yet been updated within the group's cache. When a request for the cache line is later issued by a processor, the request is issued to the system bus or interconnect. If a received response to the request indicates that the processor should utilize super-coherent data, the coherency state of the cache line is set to a processor-specific super coherency state.

Abstract: A method, system, and computer program product for generating test sequences are disclosed. Initially, a graphical user interface is invoked to display a list of preexisting test cases. A first test case is selected from the list of test cases and to create a first instance of the first test case, which is added to the test sequence. The test sequence is displayed in a test sequence portion of the graphical user interface. A subsequent test case is then selected from the list of test cases to create an instance of the subsequent test case, which is also added to the test sequence. The GUI may permit the modification of a parameter of the first test case by invoking a test case editor from the GUI. In one embodiment, the subsequent test case and the first case are the same such that first and second instances of the first test cases are included in the test sequence.

Abstract: A method of fabricating a scanning heat flow probe for making quantitative measurements of heat flow through a device under test is provided. In one embodiment the scanning heat flow probe includes an electric current conductor in a cantilever beam connected to a probe tip and coupled to two voltmeter leads. The probe also includes two thermocouple junctions in the cantilever beam electrically isolated from the electric current conductor and the two voltmeter leads. Heat flow is derived quantitatively using only voltage and current measurements. The invention also relates to the calibration of scanning heat flow probes through a method involving interconnected probes, and relates to the minimization of heat flow measurement uncertainty by probe structure design practices.

Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

Abstract: A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, and a memory controller coupled to the local interconnect and the home system memory. In response to receipt of a data request from the remote node, the memory controller transmits requested data from the home system memory to the remote node and, in a separate transfer, conveys responsibility for global coherency management for the requested data from the home node to the remote node. By decoupling responsibility for global coherency management from delivery of the requested data in this manner, the memory controller queue allocated to the data request can be deallocated earlier, thus improving performance.

Abstract: A method and apparatus for scanning the test and diagnostics control logic on a chip maintains the state of the chip in a frozen state as the scan of the normally free-running logic occurs. The chip is configured to select the test and diagnostics control logic if an instruction to scan the test and free-running logic is in the instruction register. A scan switch is configured to pass the scan output from the free-running logic to the test data output on the chip. Test data input is passed to the test and diagnostics control logic through the use of the scan select, as with the other logic units. The control interface is configured to feed a stop control and scan control signal back to the free-running logic under control of stop enable and scan enable signals. Outputs are forced to an electrically safe value by shadowing the driver control register, which controls the functional output.

Abstract: A method and apparatus is provided for enabling a static timing tool to analyze and test register files in integrated circuits to find correct paths and ignore detected contention. This is achieved by utilizing pattern matching in the static timing tool and having the tool perform certain operations on the transistors of the pattern matched. The methodology includes considering the write word lines as clock nodes, disabling signal propagation through the memory element components, forcing predetermined internal nodes to be of inverse polarity, establishing signal direction through the circuit elements, and indicating that one or more of the predetermined nodes are not to be reported.

Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die.

Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.

Abstract: A method for automatically running a plurality of interactive programs that are necessary to complete a VLSI design and verification is disclosed. Layout data is completed and saved. Multiple programs of the VLSI logic are launched using this data. The submission of design programs (jobs) operate as program “states” with each program state having data inputs, data outputs possibly receiving logic inputs and generating logic outputs. The data inputs and data outputs may be conditional in that they were generated from other program states that may not have executed error free. Logic routines generate the logic signals which are logic combinations of the generated logic outputs and these logic signals may be used to launch other program states. Once the method is started, a designer simply corrects errors that occur and then re-starts the design process.

Abstract: A method and apparatus for providing cooperative fault recovery between an operating system and a service processor allows fault detection and recovery capability utilizing a service processor while an operating system is running on a main processor. A register is provided within the main processor component for sending information to the service processor. An attention signal is provided to the service processor to indicate that the operating system has written information to the register and is requesting the service processor's attention. A JTAG standard interface is used to access the register from the service processor and an interrupt is provided to the operating system to indicate that the service processor has written information to the register and is requesting the operating system's attention.

Abstract: In a method, system, and apparatus for managing storage of data elements, a storage area having a first and second end is provided for storing the data elements. In the storage area, a first stack of data elements has first and second ends respectively facing the first and second ends of the storage area, and a second stack has data elements located proximate both ends of the first stack. That is, the second stack is split, with the first stack interposed between data elements of the second stack. Likewise, there may be a third and fourth stack, and so on, which are split into more than one part. The stacks increase in size toward both the first end of the storage area and the second end of the storage area, responsive to the storing of successive ones of the data elements in the respective stacks. Furthermore, the increasing in size of one of the split stacks may include increasing away from the first stack, or alternatively, increasing toward the first stack.

Abstract: An optical fiber link module comprises upper and lower portions and a shield. One of the upper portion or lower portion has a groove, and one of the upper portion or lower portion has at least one tab extending therefrom. The shield has a detent and at least one cutout, the detent engaging the groove and the at least one cutout cooperating with the at least one tab.

Abstract: A mobile computing device and associated base stations are disclosed. The mobile computing device includes a system-on-chip (SOC) device that includes a general purpose processor core and a plurality of peripheral cells suitable for controlling a plurality of peripheral units. The mobile computing device further includes a system memory and a base unit interface. The base unit interface is suitable for connecting the mobile computing device to a base unit that includes a display adapter suitable for controlling a video display. The SOC is connected to and enabled to control the display adapter when the mobile computing device is connected to the base unit. The base unit interface may comprise a PCI interface that connects the SOC device to the base unit via a PCI bus. The plurality of peripheral units may include an audio adapter, a flash device, a wireless suitable for transmitting and receiving wireless information, and a liquid crystal display suitable for displaying text messages.

Abstract: A method and apparatus for testing pipelined dynamic logic makes it possible to set and retrieve values from dynamic logic pipelines that have no internal latches. A modification to the pipeline circuits and clocking circuitry enable scanning logic to set and retrieve values from the pipelined circuits.

Abstract: An installation apparatus of installing a land grid array (LGA) multi-chip module assembly to a printed wiring board is provided. A module holding member is attached to the printed wiring board. The module assembly is inserted into the module holding member. The module assembly is retained to the module holding member, which facilitates mechanical actuation of the LGA compression hardware. The module assembly is electrically grounded to the printed wiring board while the module assembly is retained to the module holding member.

Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect to which a remote node and a home node are coupled. The home node contains a home system memory, and the remote node includes at least one processing unit and a cache. In response to the cache deallocating an unmodified cache line that corresponds to data resident in the home system memory, a cache controller of the cache issues a deallocate operation on a local interconnect of the remote node. In one embodiment, the deallocate operation is further transmitted to the home node via the node interconnect only in response to an indication, such as a combined response, that no other cache in the remote node caches the cache line. In response to receipt of the deallocate operation, a memory controller in the home node updates a local memory directory associated with the home system memory to indicate that the remote node does not hold a copy of the cache line.

Abstract: System bus masters within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the historical access information for the target cache line to their requests. Snoopers and/or the system controller, which may also maintain dynamic application sequence behavior information in a history directory, employ the appended access information for cache management.