Abstract: A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes an electrical conductor thermally coupled to a cold plate and a thermoelement electrically coupled to the electrical conductor. The thermoelement is constructed from a thermoelectric material and has a plurality of tips through which the thermoelement is electrically coupled to the electrical conductor. The thermoelectric tips provide a low resistive connection while minimizing thermal conduction between the electrical conductor and the thermoelement.

Abstract: An apparatus for accessing a banked embedded dynamic random access memory device is disclosed. The apparatus for accessing a banked embedded dynamic random access memory (DRAM) device comprises a general functional control logic and a bank RAS controller. The general functional control logic is coupled to each bank of the banked embedded DRAM device. Coupled to the general functional control logic, the bank RAS controller includes a rotating shift register having multiple bits. Each bit within the rotating shift register corresponds to each bank of the banked embedded DRAM device. As such, a first value within a bit of the rotating shift register allows accesses to an associated bank of the banked embedded DRAM device, and a second value within a bit of the rotating shift register denies accesses to an associated bank of the banked embedded DRAM device.

Abstract: An instruction fetching system (and/or architecture) which may be utilized by a high-frequency short-pipeline microprocessor, for efficient fetching of both in-line and target instructions. The system contains an instruction fetching unit (IFU), having a control logic and associated components for controlling a specially designed instruction cache (I-cache). The I-cache is a sum-address cache, i.e., it receives two address inputs, which compiled by a decoder to provide the address of the line of instructions desired fetch. The I-cache is designed with an array of cache lines that can contain 32 instructions, and three buffers that each have a capacity of 32 instructions.

Abstract: A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.

Abstract: In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access and snoop operation information for the corresponding cache line. The historical processor access and snoop operation information includes different subentries for each different processor which has accessed the corresponding cache line, with subentries being “pushed” along the stack when a new processor accesses the subject cache line. Each subentries contains the processor identifier for the corresponding-processor which accessed the cache line, a processor access history segment, and a snoop operation history segment. The processor access history segment contains one or more opcodes identifying the operations which were performed by the processor, and timestamps associated with each opcode.

Abstract: A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized.

Abstract: A thermoelectric cooling system integrating quantum cold point connections with lateral thermoelectric element formation. A preferred system has an n-type and p-type thermoelectric element, each connected to a common conducting section. The thermoelectric elements are each tapered at the end where they contact the common conducting section. The thermoelectric elements preferably all occupy substantially the same plane as each other and as the common conducting section.

Abstract: A system for and method of monitoring memory transactions in a data processing system are disclosed. The method includes defining a set of memory transaction attributes with a monitoring system and detecting, on a data processing system connected to the monitoring system, memory transactions that match the defined set of memory transaction attributes. The number of detected memory transactions occurring during a specified duration are then displayed in a graphical format. In one embodiment, the data processing system comprises a non-uniform memory architecture (NUMA) system comprising a set of nodes. In this embodiment, the detected transactions comprise transactions passing through a switch connecting the nodes of the NUMA system. The set of memory transaction attributes may include memory transaction type information, node information, and transaction direction information.

Abstract: A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.

Abstract: A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space. In one preferred embodiment, the execution units of the processor include a number of load-store units (LSUs) that each process only instructions that access data having associated addresses within a respective one of the plurality of address subsets. The processor may further be incorporated within a data processing system having a number of interconnects and a number of sets of system memory hardware that each have affinity to a respective one of the plurality of address subsets.

Abstract: A read/write head cooling system for use in a magnetic storage device, such as, for example, a hard disk drive is provided. In one embodiment, a thermally conducting patterned cold plate is thermally situated between a write coil and a read sensor of the read/write head. A microcooler, such as, for example, a thermoelectric cooler, is thermally coupled to the cold plate. A hot plate of one or more heat dissipation elements, such as, for example, copper posts, is thermally coupled to the hot side of the microcooler. The write coils of the read/write head are actively cooled by the microcooler to reduce the temperature of the write coil and read sensor in the head below that attainable with passive mechanisms.

Abstract: Apparatus and methods for performing switching of heat flow in magnetic refrigeration systems are provided. In one embodiment, microelectromechanical (MEM) switches are provided for switching from a heat absorption phase and a heat rejection phase of a magnetic refrigeration cycle. In other embodiments, these MEM switches are replaced by thermoelectric switches. The thermoelectric switches operate such that an “on” state is defined as heat flow being allowed by virtue of the thermal conductivity of the thermoelectric switch. An “off” state is defined as a net zero heat flow through the thermoelectric switch obtained by providing a current that is just sufficient to offset the heat flow through the thermoelectric switch due to its thermal conductivity. In some embodiments, the thermoelectric switches are “directly coupled” thermoelectric switches, meaning that they are energized by a direct electrical coupling to a current source.

Abstract: A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.

Abstract: Apparatus and methods for performing switching of heat flow in magnetic refrigeration systems are provided. In one embodiment, microelectromechanical (MEM) switches are provided for switching from a heat absorption phase and a heat rejection phase of a magnetic refrigeration cycle. In other embodiments, these MEM switches are replaced by thermoelectric switches. The thermoelectric switches operate such that an “on” state is defined as heat flow being allowed by virtue of the thermal conductivity of the thermoelectric switch. An “off” state is defined as a net zero heat flow through the thermoelectric switch obtained by providing a current that is just sufficient to offset the heat flow through the thermoelectric switch due to its thermal conductivity. In some embodiments, the thermoelectric switches are “directly coupled” thermoelectric switches, meaning that they are energized by a direct electrical coupling to a current source.

Abstract: A method and system for controlling the purchase of fine-grained resource purchases, such as utility resources or access to limited highway lanes. Real time pricing based upon current demand and/or usage is periodically determined. Access to that real time pricing information is obtained by individual users via a distributed computing network or radio frequency broadcast system and utilization of those resources is then locally controlled based upon that pricing information. Access to limited highway lanes may be priced based upon current actual utilization and pricing information is then broadcast, permitting users to selectively access those lanes based upon real time pricing decisions by those users.

Abstract: A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of snoop responses from the bus accessible memory devices are provided. Different transfer types are provided within each of the snoop response groups. A bus master device that provides a bus master signal is designated. The bus master device receives the processor request. One of the snoop response groups and one of the transfer types are appropriately designated based on the processor request. The bus master signal is formulated from a snoop response group, a transfer type, a valid request signal, and a cache line address. The bus master signal is sent to all of the bus accessible memory devices on the cache bus line and to a combined response logic system.

Abstract: A data processing system includes an interconnect, a plurality of nodes coupled to the interconnect that each include at least one agent, response logic within each node, and a queue. In response to snooping a transaction on the interconnect, each agent outputs a snoop response. In addition, the queue, which has an associated agent, allocates an entry to service the transaction. The response logic within each node accumulates a partial combined response of its node and any preceding node until a complete combined response for all of the plurality of nodes is obtained. However, prior to the associated agent receiving the complete combined response, the queue speculatively deallocates the entry if the partial combined response indicates that an agent other than the associated agent will service the transaction.

Abstract: Apparatus and methods for performing switching of heat flow in magnetic refrigeration systems are provided. In one embodiment, microelectromechanical (MEM) switches are provided for switching from a heat absorption phase and a heat rejection phase of a magnetic refrigeration cycle. In other embodiments, these MEM switches are replaced by thermoelectric switches. The thermoelectric switches operate such that an “on” state is defined as heat flow being allowed by virtue of the thermal conductivity of the thermoelectric switch. An “off” state is defined as a net zero heat flow through the thermoelectric switch obtained by providing a current that is just sufficient to offset the heat flow through the thermoelectric switch due to its thermal conductivity. In some embodiments, the thermoelectric switches are “directly coupled” thermoelectric switches, meaning that they are energized by a direct electrical coupling to a current source.

Abstract: An apparatus for cooling selected elements within an integrated circuit, such as active transistors or passive circuit elements used in a radio frequency integrated circuit is provided. In one embodiment, the cooling apparatus includes a cold plate thermally coupled to the region proximate the integrated circuit element, a thermoelectric cooler thermally coupled to the cold plate; and a hot plate thermally coupled to the thermoelectric cooler. Heat is removed from the integrated circuit element through the cold plate and transmitted to the hot plate through the thermoelectric cooler. In one form, the hot plate is located or coupled to an exterior surface of an integrated circuit, such that heat transmitted to the ambient from the integrated circuit element is dissipated into the atmosphere surrounding the integrated circuit. In another form, the hot plate is embedded in the integrated circuit substrate to locally cool elements of the integrated circuit while dumping the heat into the substrate.