Abstract: A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.

Abstract: The enhanced folded flexible cable packaging for use in optical transceivers of the present invention provides a 90 degree transition between an optical signal input/output at a communication chassis bulkhead, and folds 180 degrees around a horizontal heat spreader to provide the capability to wire electrical components to the flexible cable while maintaining the upper surface of the electrical components in close proximity to a heat sink. This allows signals to be processed through a multi-layer flexible cable providing electrical performance without the mechanical stiffness associated with the bends that occur in the package. The multiple array transceiver makes the 90 degree transition within a narrow gap established by industry and manufacturing standards. The multiple array transceiver also provides cooling to the internal electronics through a heat sink attached to the flexible cable and the heat spreader, which concurrently mounts and locates the transceiver to a common host board.

Abstract: A system and method for synchronizing a set of nodes connected to a central switch in a multi-node data processing system, such as a NUMA data processing system, are disclosed. Initially, time base register values are retrieved from each of the set of nodes. A common time base register value is then determined based upon the time base register values received from the nodes. The common time base register value that is determined is then broadcast to each of the nodes. Prior to reading the time base register values, packet traffic among the set of nodes may be halted by broadcasting a halt traffic packet to each of the nodes. In this embodiment, normal packet traffic may be resumed after synchronization by broadcasting a resume traffic packet to each of the nodes. The time base register values may be read by issuing a special purpose interrupt from a node adapter to one of the node processors in response to the adapter receiving a read time base packet from the switch.

Abstract: A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry response, a determination is made whether or not the Retry response was caused by a target snooper that will service the memory access request. If not, the target snooper services the memory access request in spite of the Retry response. In a preferred embodiment in which the memory access request is a write request and the target snooper is a memory controller, stale data cached by at least one snooper in association with the address are also invalidated by a snooper, such as the memory controller, transmitting at least one address-only kill transaction on the interconnect. Advantageously, the address-only kill transaction can be issued concurrently with or following servicing the write request so that the write request does not incur latency by waiting until all stale copies of the data have been invalidated.

Abstract: During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.

Abstract: A scanning heat flow probe for making quantitative measurements of heat flow through a device under test is provided. In one embodiment the scanning heat flow probe includes an electric current conductor in a cantilever beam connected to a probe tip and coupled to two voltmeter leads. The probe also includes two thermocouple junctions in the cantilever beam electrically isolated from the electric current conductor and the two voltmeter leads. Heat flow is derived quantitatively using only voltage and current measurements. In other forms, the invention relates to the calibration of scanning heat flow probes through a method involving interconnected probes, and relates to the minimization of heat flow measurement uncertainty by probe structure design practices.

Abstract: An apparatus for allocating data usage in an embedded dynamic random access memory (DRAM) device is disclosed. The apparatus for allocating data usages within an embedded dynamic random access memory (DRAM) device comprises a control analysis circuit, a data/command flow circuit, and a partition management control. The control analysis circuit generates an allocation signal in response to processing performances of a processor. Coupled to an embedded DRAM device, the data/command flow circuit controls data flow from the processor to the embedded DRAM device. The partition management control, coupled to the control analysis circuit, partitions the embedded DRAM device into a first partition and a second partition. The data stored in the first partition are different from the data stored in the second partition according to their respective usage. The allocation percentages of the first and second partitions are dynamically allocated by the allocation signal from the control analysis circuit.

Abstract: A method and apparatus performing rotate operations using cascaded multiplexers provides a scalable rotator circuit having a sub-field rotate capability that requires no additional interconnects at the sub-field endpoints. The rotator performs bit field swap operations at each stage of a series of cascaded multiplexers. The bit field size increases monotonically from a single bit to half of the rotator operand size. The control logic selects swap operations for each individual bit field at each stage, in order to arrange a desired rotated output vector.

Abstract: A behavioral memory mechanism for performing fetch prediction within a data processing system is disclosed. The data processing system includes a processor, a real memory, an address converter, a fetch prediction means, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The address converter converts an effective address to an architecturally visible virtual address and a behavioral virtual address. The architecturally visible virtual address is utilized to access the architecturally visible virtual memory region of the virtual memory and the behavioral virtual address is utilized to access the behavioral virtual memory region of the virtual memory.

Abstract: A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.

Abstract: A method of designing the layout of an integrated circuit (IC) by deriving an analytical constraint for a cut-based placement partitioner using analytical optimization, and placing cells on the IC with the cut-based placement partitioner using the analytical constraint. Quadratic optimization may be used to determine a desired ratio of a cell area of a given partition to a total cell area (the balance parameter), and placing may be performed using multilevel bisection partitioning constrained by the balance parameter. This implementation may include a determination of an aspect ratio for an entire partitioning region of the integrated circuit, and a “center-of-mass” coordinate of the cells based on the quadratic optimization, which are then used to define a placement rectangle having the same aspect ratio, and centered on the center-of-mass coordinate. This placement rectangle is used to derive the balance parameter.

Abstract: A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency.

Abstract: An optical fiber link module adapted to receive a fiber optic cable. The optical fiber link module comprises a multiple array lens and a female connector. The female connector is disposed around the multiple array lens, and has an internal cavity. An electromagnetic shield is disposed in the internal cavity, and has a single central aperture sized to permit communication by the multiple array lens through the central aperture.

Abstract: A bidirectional bus and data processing system suitable for suppressing cross talk noise are disclosed. The bidirectional bus includes, a first interconnect line driven by a pair of drivers, a first pair of impedance elements connected between the first line and a second line of the bus, and a second pair of impedance elements connected between the first line and a third line of the bus. In one embodiment, the capacitive coupling per unit length between the first line and the second line is approximately equal to k and the impedance of the first pair of impedance elements is approximately equal to (&ugr;k)−1, where &ugr; is the speed of light through a dielectric in which the first and second lines are located. In one embodiment, the impedance of the first driver is approximately equal to (&ugr;c0)−1, wherein c0 is the self-capacitance of the first line.

Abstract: A process for efficiently computing moments in an interconnected circuit begins by partitioning the circuit into sets of line-like two-port circuits. Next, capacitors are converted to equivalent current sources and inductors are converted to equivalent voltage sources. From a first port, any connected voltage source which is present in line is added to the port voltage source. Then, that voltage source combined with the connected resistor and the Thevenin equivalent circuit is converted to a Norton equivalent circuit. The current source created from the conversion is added to a current source in the circuit and the Norton equivalent circuit is converted back to a Thevenin equivalent circuit. The process is recursively performed until the opposite port is reached. The moment is then computed from the final Thevenin equivalent circuit by using the voltage and current at the port. The Thevenin-Norton-Thevenin recursive process is then repeated for the opposite port.

Abstract: A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

Abstract: A method and system is disclosed for software manipulation of hardware prediction mechanism in a data processor with software prediction. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits are settable by a software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of said instruction is predicted based on the value of the bits.

Abstract: A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be used to provide a unique 1-bit signal to each bus agent indicating whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit.

Abstract: The packaging architecture for a multiple array transceiver using a winged flexible cable for optimal wiring of the present invention provides a 90-degree transition between an optical signal input/output at a communication chassis bulkhead, and provides an attachment to a heat spreader for use in wiring electrical components to the flexible cable. The packaging architecture system comprises a forward vertical carrier having an optical converter, a rearward horizontal I/O block oriented about 90 degrees from the forward vertical carrier, a heat spreader, and a flexible cable attached to the sides of the heat spreader. The multiple array transceiver makes the 90-degree transition within a narrow gap established by industry and manufacturing standards. The multiple array transceiver also provides cooling to the internal electronics through a heat sink that is attached to the heat spreader which concurrently mounts and locates the transceiver to a common host board.

Abstract: A method and system for detecting authorized programs within a data processing system. The present invention creates a validation structure for validating a program. The validation structure is embedded in the program and in response to an initiation of the program, a determination is made as to whether the program is an authorized program. The determination is made using the validation structure.