Abstract: A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.

Abstract: A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines.

Abstract: An electron beam photolithographic process for patterning an insulation layer over a substrate. A conductive photoresist layer having a conjugate structure is formed over the insulation layer. An electron beam photolithographic process is conducted using a photomask so that the pattern on the photomask is transferred to the conductive photoresist layer.

Abstract: An overlay mark for concurrently monitoring alignment accuracy, focus, leveling and astigmatism and a method of application thereof are disclosed. The overlay mark comprises four inner bars and four outer bars formed at the corners of exposure areas. The inner bar has a sawtooth area and a bar-shaped area, and the outer bar is a fore-layer etched pattern. Both the inner bars and the outer bars are formed into rectangles, and each bar is one side of a rectangle and none of the sides are connected. The sawtooth areas of the inner bars disposed on opposite sides are located at a same position. The rectangle formed by the outer bars encloses the rectangle formed by the inner bars. During the monitoring process, a testing beam scans across a scan area being divided into two areas, i.e., one being the outer bars and the sawtooth area of the inner bars, and the other one being the outer bars and the bar-shaped area of the inner bars.

Abstract: A method of fabricating a self-aligned shallow trench isolation. A mask layer, two deep trenches and two internal electrodes of a capacitor are sequentially formed on a substrate. Two conductive layers are used to completely fill the two deep trenches. Then, two spacers are formed on exposed sides of the two conductive layers, and two doped regions are formed in a portion of the substrate located next to the two conductive layers. A patterned photoresist layer is formed to expose at least the spacers located in between the two deep trenches and the mask layer. The photoresist layer and the spacers are utilized as masks to etch away the exposed mask layer. The photoresist layer is utilized again as a mask to etch the exposed spacers and a portion of the exposed substrate. Sequentially, a remained portion of the photoresist layer and a portion of the conductive layers are removed. A remained mask layer is used as a mask to remove a portion of the exposed substrate, and a trench is thus formed.

Abstract: A method of forming the lower electrode of a capacitor capable of withstanding the flushing force produced by a cleaning agent. A lower electrode having a rectangular profile when viewed from the top is provided. The lower electrode is bounded by a pair of ends and a pair of sides. The ends and the sides are linked together. The ends have a wedge shape. The sides have edges that cave in towards the center, thereby forming a recess region between the sides. A flushing operation is carried out using a cleaning solution. The cleaning solution flows from one end of the electrode to the other end along the sides.

Abstract: A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.

Abstract: A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.

Abstract: A double-bit non-volatile memory cell structure and a method of programming the memory cell. The memory cell includes a pair of stacked gates above a substrate, a doped region in the substrate between the stacked gate pair and a source/drain region in the substrate on each side of the stacked gate pair. The source/drain regions and the doped region are doped identically. To write data into the memory cell, the channel underneath both stacked gates is opened simultaneously. Data is written into the desired floating gate by controlling current flow direction. To read data from a first floating gate of the memory cell, a read bias voltage is applied to the first control gate above the first floating gate. In the meantime, a transfer voltage is applied to the second control gate. The presence or the absence of a conductive channel between the source/drain regions indicates whether data has been written into the first floating gate or not.

Abstract: A temperature controlling protection system for a heater of the wet etching device has a temperature controlling protection circuit and a heating ON/OFF controller, in which the temperature controlling circuit has an OR gate, an AND gate and a NOT gate. When the temperature controlling protection circuit receives signals from the wet etching device, such as a level signal for a level sensor, an overheated signal for a temperature sensor, a ON/OFF signal for an acid discharging switch, a protection signal and a caution signal for the heater 28 and output signal for a constant temperature controller, it is determined whether the heater of the wet etching device is actuated to provide heat to the reaction gas in the wet etching device.

Abstract: A conductive structure in a silicon wafer for preventing plasma damage. The wafer includes a plurality of dies and a plurality of scribe lines between the dies. The semiconductor substrate of this wafer further includes a plurality of patterned conductive layers. The conductive structure comprises of a plurality of ground wires and a plurality of contacts. The ground wires are distributed inside the scribe lines and are positioned at least in the uppermost conductive layer. The contacts are used for connecting the ground wires and the semiconductor substrate electrically. When other conductive layers other than the uppermost conductive layer also contain ground wire connections, the ground wires in different conductive layers are electrically connected by plugs.

Abstract: A radiation detection device for locally detecting radiation of RF energy emissions from close proximity direct line-of-sight electromagnetic fields emitted by a wireless transmit/receive electronic equipment antenna 22 or body 21 such as a cellular telephone, in miniature/planar design form with suitable embedding form-factoring fashioned arrangement capability joined with radiation shielding devices. Said radiation detection device operates without prerequisite need for a battery or external power source, operationally self-powered by the embodiments of this invention when exposed to electromagnetic field radiation of predetermined thresholding energy level setting for the user's own personal alerting verification and assessment means of suitable predetermined radiation detection measurement tester coupling to radiation shielding devices to encompass an overall shield effectiveness system solution in real-time monitoring response fashion operation.

Abstract: A thermal flow photolithographic process. A thermal flow photoresist is provided. A cross-linking agent is added to the thermal flow photoresist to form a high-temperature cross-linking photoresist material. A substrate having an insulation layer thereon is provided. The high-temperature cross-linking photoresist is deposited over the insulation layer. The cross-linked photoresist layer on the insulation layer is exposed to light, chemically developed and then heated to cause thermal flow.

Abstract: A selective memory refresh circuit for refreshing a memory cell array. The memory cell array has a plurality of word lines connected to a plurality of word line selection circuits for determining if a particular word line needs to be refresh during a refresh cycle. Each word line refresh selection circuit further has a word line address latching device for receiving a word line pre-decode signal, a release signal, a triggering signal and outputting a word line latching signal and a word line refresh compare circuit for receiving the word line pre-decode signal and the word line latching signal and transmitting the result of comparison to a word line driver. When the word line latching signal is at a high level, memory cells attached to the word line are refreshed. On the contrary, when the word line latching signal is at a low level, memory refresh for that word line is skipped.

Abstract: A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Abstract: A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening opening after the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses.

Abstract: A method of reworking a photoresist layer. A silicon chip having an insulation layer, a bottom anti-reflection coating and a photoresist layer thereon is provided. The photoresist layer has already been light-exposed and developed. A wet etching operation is carried out to remove a large portion of the photoresist layer. A low-temperature plasma treatment incapable of transforming the anti-reflection coating structure is conducted to remove the hardened residual photoresist material. A new photoresist layer is formed over the bottom anti-reflection coating.

Abstract: An optical proximity correction method. Assist features, such as scattering bars, are added to a main pattern to be transferred. Calculations are performed on the entire two-dimensional original pattern using model-based optical proximity correction. A series of features are added according to the specific reference indexes of the coordinate system. The original pattern is altered to form a corrected pattern. The process of calculation and correction, however, does not include the scattering bars.

Abstract: A floating body ESD protection circuit positioned between and coupled to an I/O pad and an internal circuit. A p-type depletion mode transistor is used to control the body of an n-type enhancement mode transistor. When the p-type depletion mode transistor is triggered, the body of n-type enhancement mode transistor remains grounded. If the p-type depletion mode transistor has not been triggered, the body remains in a floating state, lowering the range of the snapback voltage. As a consequence the ESD protection circuit is able to function more rapidly. Similarly, an n-type depletion mode transistor is used to control the body of a p-type enhancement mode transistor. When the n-type depletion mode transistor is triggered, the body remains coupled to a high voltage. If the n-type depletion mode transistor has not been triggered, the body is in a floating state. Thus, the range of the snapback voltage can be lowered, enabling the ESD protection circuit to function more rapidly.

Abstract: A wrench having two driving stems pivotally connected with each other. One of the driving stems has a main stem and a female joint protruding from a rectangular or cylindrical section of the main stem with a hole at a center thereof. The other driving stem has the other main stem and a male joint projecting out of the center of a rectangular or cylindrical section of the main stem. The male joint and the female joint are engaged with each other via a coupler such as a roll pin. Therefore, without using an additional hinge or other mechanical coupler, these two driving stems are pivotally connected with each other.