Abstract: A static random access memory manufacturing method. A substrate having a gate oxide layer and a first conducting layer is defined to form a buried contact window opening. A second conducting layer is formed upon the substrate with a recess structure at the region of the buried contact opening. A buried contact window is formed in the substrate under the buried contact window opening. A protective layer is formed upon the substrate and fills the recess. A portion of the protective layer is removed, and a patterned photoresist layer is formed upon the substrate. Using the photoresist as a mask, the first and second conducting layer are etched to form a gate electrode and an interconnect. The patterned photoresist layer is removed. The protective layer can be removed or retained. An implantation procedure is performed, thereby forming a source/drain, thereby connecting the source/drain and the contact window.

Abstract: A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines.

Abstract: A voltage supply control apparatus, suitable for being applied to a low voltage operation device. The voltage supply control apparatus has a high threshold voltage transistor and a low threshold voltage transistor. When the low voltage operation device is not working, the low threshold voltage transistor is cut off, and the voltage drop of a high voltage received from the power source terminal of the low voltage operation device is controlled by the high threshold voltage transistor. In contrast, when the low voltage operation device is working, the operation enable signal output thereby conducts the low threshold voltage transistor to control the voltage drop of the high voltage received from the power source terminal, so that a high potential is obtained.

Abstract: A contact hole model-based optical proximity correction method. The method includes building a contact hole model from the database obtained through a series of test patterns each having a plurality of contact holes of different line widths but identical distance of separation. Line width offsets due to proximity effect are eliminated by referring to the contact hole model.

Abstract: An alignment mark design has a metal plateau and a metal material formed over a substrate. The metal plateau is within a first dielectric layer. Openings within a second dielectric layer above the first dielectric layer are filled with a metal material. The metal material and the second dielectric layer alternate so that a part of the exposure light passing through the second dielectric layer between sections of the metal material can be reflected into an alignment system by the metal plateau.

Abstract: A detecting device for monitoring any abnormality in chemical-mechanical polishing. The detecting device includes a motor, an inverter, a control circuit, a rotation sensor, a current sensor, a relay controller and a chemical-mechanical controller. The inverter converts a direct current into an alternating current for driving the motor. The control circuit controls size and functioning of the output alternating current from the inverter. The rotation sensor is a transducer for converting the running speed of the motor into a rotation signal and transmitting the signal to the control circuit. The current sensor monitors the size of the alternating current flowing to the motor and then outputs a current signal. The relay controller receives the current signal from the current sensor and outputs a drive signal. The chemical-mechanical polishing controller receives the drive signal from the relay controller and outputs a system halt signal to the control circuit.

Abstract: A method of fabricating a bottom electrode is described. A substrate having a conductive layer therein is provided. A first dielectric layer is formed over the substrate. A conductive plug is formed through the first dielectric layer to electrically couple with the conductive layer. A cap layer is formed over the substrate to cover the conductive plug. An isolation layer is formed over the cap layer. A plurality of bit lines is formed over the isolation layer. A second dielectric layer is formed over the isolation layer. A node contact opening is formed through the second dielectric layer, the bit lines and the isolation layer to expose the cap layer. A conformal isolation layer is formed over the substrate to partially fill the contact node opening. A third dielectric layer having an opening is formed over the substrate. The opening is aligned with the node contact opening. An etching step is performed to remove a portion of the conformal isolation layer exposed by the opening and the cap layer.

Abstract: A method of forming a self-aligned stacked capacitor on a substrate having a first insulation layer thereon. A bit line contact and a first section node contact are formed in the first insulation layer, and then a bit line structure is formed over the first insulation layer. The bit line structure includes a bit line, a cap layer and spacers. The bit line and the bit line contact are electrically connected. The cap layer is formed above the bit line while the spacers are formed on the sidewalls of the bit line and the cap layer. A second insulation layer, an etching stop layer and a third insulation layer are sequentially formed over the substrate. An opening is formed in the third insulation layer, the etching stop layer and the second insulation layer to expose a portion of the bit line structure and the first section node contact. A conformal first conductive layer is formed over the interior surface of the opening.

Abstract: A method of forming a local interconnect contact opening is described. A liner layer is formed on a substrate having a gate structure, a first source/drain region, and a second source/drain region formed thereon. A planarized dielectric layer is formed over the liner layer. A photoresist layer, which defines the location of the local interconnect contact opening, is formed over the dielectric layer. A one-step etching process is performed using a C5F8/CO/O2/Ar etching gas and the liner layer as an etching stop. The dielectric layer exposed by the opening of the photoresist layer is removed to expose the liner layer. The liner layer and the photoresist layer are removed.

Abstract: A method of forming a dynamic random access memory. A substrate having a memory cell region and a logic circuit region is provided. The substrate also has a first dielectric layer thereon. The first dielectric layer in the memory cell region has a bit line and a node contact while the first dielectric layer in the logic circuit region has a first metallic interconnect. An intermediate dielectric layer is formed over the first dielectric layer such that the intermediate dielectric layer in the logic circuit region has a second metallic interconnect that connects electrically with the first metallic interconnect. A capacitor is formed in the intermediate dielectric layer within the memory cell region. A second dielectric layer is formed over the substrate. A third metallic interconnect is formed in the second dielectric layer such that the third metallic interconnect and the second metallic interconnect are electrically connected.

Abstract: A method of fabricating a buried contact. On a substrate having a shallow trench isolation thereon, a gate oxide layer and a polysilicon layer are sequentially formed. The polysilicon layer and the gate oxide layer are patterned to expose a portion of the substrate. A diffusion region is formed in the exposed substrate. On the polysilicon layer and the exposed diffusion region, an amorphous silicon layer is formed. Consequently, a native oxide layer is formed between the polysilicon layer and the amorphous silicon layer, and between the amorphous silicon layer and the diffusion region. An anti-reflection coating layer is formed on the amorphous silicon layer. Using the native oxide layer as an etching buffer, the anti-reflection coating layer and the amorphous silicon layer are patterned until the diffusion region and the polysilicon layer are exposed.

Abstract: A method of removing silicon carbide. A silicon wafer is used as a dummy wafer for inspecting the properties of a silicon carbide thin film which is to be formed thereover. A silicon nitride layer with a thickness larger than about 1000 angstroms is formed on the dummy wafer as a base layer of the silicon carbid thin film. The silicon carbide thin film is then formed on the base layer. The property inspection of the silicon carbide thin film is performed. After the properties inspection, the silicon carbide is stripped using a high density hydrogen plasma. After the step of high density hydrogen plasma, if the remaining silicon nitride layer is thicker than about 500 angstroms, the remaining silicon nitride layer can be used as the base layer again for forming and inspecting the properties of the silicon carbide thin film.

Abstract: An array-type layout for a silicon on insulator (SOI) transistor. A body contact region of the first conductive type is provided. A polysilicon gate structure is arranged in array over the body contact region. The polysilicon gate structure divides the body contact region into an array of alternating source regions of a second conductive type and drain regions of a second conductive type.

Abstract: A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

Abstract: An alternate-timing burn-in method suitable for testing a plurality of memory units on a wafer and capable of preventing any idling due to direct current timing. A first bit line voltage clocking signal is generated and sent to one terminal of any memory unit. A second bit line voltage clocking signal is generated and sent to the other terminal of the same memory unit. In addition, the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.

Abstract: A method for stripping a low dielectric film with a high carbon content from silicon monitor chip. The silicon monitor chip is placed inside a plasma-enhanced chemical vapor deposition chamber and the surface is treated with oxygen plasma to form a silicon-rich oxide layer. A high-carbon-content low dielectric film is formed over the silicon-rich oxide for film quality inspection. After the film inspection, the silicon monitor chip is immersed in a solution containing ammonium hydroxide and hydrogen peroxide so that the surface of the high-carbon-content dielectric film is transformed from hydrophobic to hydrophilic. Hence, wetting capacity of subsequently applied hydrofluoric acid solution is enhanced. Finally, the silicon monitor chip is immersed in a hydrofluoric acid solution for stripping away the low dielectric film.

Abstract: A method of fabricating a self-aligned contact (SAC) and gate structure is described. A gate oxide layer, a conductive gate a cap layer and a source/drain are formed on a substrate. A conformal buffer layer is formed. An undoped polysilicon spacer is formed. A dielectric layer is formed over the substrate. Photolithography and etching technologies are used to form a self-aligned opening in the dielectric layer and conformal buffer layer. The self-aligned contact opening is filled with a conductive layer, to form a self-aligned contact.

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: A method of testing EM lifetime has following steps. First, a pre-characterizing step is performed to obtain parameters such as TC(the critical temperature,), Wc (the critical line width), QGB(the activation energy of grain boundary diffusion) and QL(the activation energy of lattice diffusion) of a metal prior to the use of the test methodology for a new technology. Next, whether a real line width (W) of the metal is narrower or wider than WC is determined. For the narrower line widths, the diffusion mechanism is dominated by the Lattice diffusion only and corresponds to single activation energy (QL). A WLR isothermal test with a relatively high temperature, such as 400° C., can be implemented to reduce the test time to as short as a few seconds. The EM lifetime (t50) under normal operating condition can be directly obtained by conversion from Ttest to TC by using QL.