Abstract: A method of fabricating a static random access memory. A stacked gate is formed on a substrate. A lightly doped drain region and a lightly doped source region are formed in the substrate. A thin spacer is then formed on a sidewall of the stacked gate on the lightly doped source region only. However, this thin spacer does not completely cover the lightly doped source and drain regions, that is, portions of the light doped source and drain regions are exposed. A thick spacer is then formed on the other sidewall of the stacked gate on the lightly doped drain region only. Using both the thin and the thick spacers as a mask, an ion implantation is performed to form a heavily doped source region and a heavily doped drain region in the substrate. A self-aligned silicide step is performed to form a salicide layer on the stacked gate, the source and the drain regions.

Abstract: A photolithographic process for preventing the rounding of the corners of a pattern. A silicon wafer is provided. A first photoresist layer is formed over the silicon wafer and then patterned to form a first group of mutually parallel photoresist lines along a first direction. A second photoresist layer is formed over the silicon wafer and then patterned to form a second group of mutually parallel photoresist lines along a second direction. The first direction and the second direction are on the same plane but mutually perpendicular.

Abstract: A method for fabricating a thin film resistor is provided. The method contains forming a patterned conductive layer on a dielectric layer, which is formed over a substrate having a semiconductor device. The patterned conductive layer has a first opening to expose a portion of the substrate. An insulating layer is formed over the substrate and is planarized, in which the first opening is filled by the insulating layer. Patterning the insulating layer forms a second opening that exposes the first opening and a portion of the patterned conductive layer at a place, where a thin film resistor is desired to be formed. A thin film resistor conformal to the second opening is formed over the dielectric layer to at least cover the opening.

Abstract: A wrench comprising two driving stems pivotally connected with each other. One of the driving stems has a main body and a flat portion, protruding from the main body with a hole at a center thereof. The other driving stem has the other main body and the other flat portion protruding from the other main body with at a center thereof. A pair of hinges having two holes aligned with the holes of the flat portions protruding from the main bodies of the driving stems, respectively, is used. Two sets of bolts and nuts are used to be threaded through the holes of the hinges, the flat portion protruding from main bodies of the first and the second driving stems, respectively.

Abstract: A method of automatically forming a rim PSM is provided. A first pattern comprising a conventional original pattern as a blinding layer and assist features around the conventional circuit pattern is designed. A portion of a Cr film and a portion of a phase shifting layer under the Cr film are removed with the first pattern. The removed portion of the Cr film and the removed portion of the phase shifting layer are positioned on the assist feature. A second pattern comprising the conventional circuit pattern and a half of the assist features is designed. A portion of the Cr film in positions other than on the second pattern is removed. The convention circuit pattern formed at the mask medium is defined as the blinding layer. The area of the assist features only comprise a quartz substrate that light can pass through. The other areas of the mask medium wherein the phase shifting layer remains is defined as the phase-shifting portion of the PSM.

Abstract: A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.

Abstract: A jet-cleaning device for a developing station is proposed, which jet-cleaning device is capable of removing chemical solution from the back surface of a silicon wafer without the need to perform time-consuming adjustment of knife ring position. The jet-cleaning device has a spin suction pad, a plurality of air nozzles and knife ring. The spin suction pad is used to support a silicon wafer. The spin suction pad has an external diameter smaller than the silicon wafer so that an peripheral portion of the wafer back surface is exposed. The plurality of air nozzles are positioned under the spin suction pad and mounted on a substrate plate. The air nozzles send out air jets directing at the exposed back surface of the wafer so that any dripping chemical solution can be blown away. The knife ring is installed under the wafer around the spin suction pad to prevent the sputtering of chemical solution back into the spin suction pad.

Abstract: A semiconductor memory device and a method for mending a failed memory cell by directly programming a fuse memory cell. Using a tester to program the fuse memory cell directly, a laser machine is not required. In addition, to move the wafer for fuse allocation is not required either, so that the consumption in time and cost can be greatly reduced. Even after the package is complete, the repairing work can still be performed. In addition, whether the voltage source is connected or disconnected, the failed address information is kept and stored without being lost. A self-repair for self-test can thus be applied.

Abstract: A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

Abstract: A fabrication method for an air-gap, in which method hard mask is used, is described. A patterned hard mask layer is formed on a semiconductor substrate. Taking advantage of the etching selectivity of the hard mask layer to the dielectric layer, an opening with a high aspect ratio is formed in the dielectric layer. A conductive plug is then formed in the opening, followed by forming a conductive layer on the hard mask layer to cover the conductive plug. The hard mask layer is further removed. A silicon oxide layer with poor step coverage is formed to cover the substrate. Using the space remaining after the removal of the hard mask layer, an air-gap is formed between the conductive layer and the dielectric layer to enhance the insulation effect.

Abstract: A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.

Abstract: A method to reduce the inverse-narrow-line-effect is described in which an active region and an isolation region are defined on a substrate. A doped region is formed adjacent to the substrate surface, wherein the area of the doped region includes the isolation region and the edge of the active region. The depth of the doped region is shallower than that of the source/drain region formed subsequently. A shallow trench is formed thereafter in the isolation region adjacent to the active region, such that the doped region located in the substrate at the edge of the active region is retained. A liner oxide layer is further formed on the inner wall of the shallow trench. An oxide layer, which is as high as the surface of the cap layer, is formed to fill the trench. After the removal of the pad oxide layer and the cap layer, a gate oxide layer and a gate are formed on the substrate.

Abstract: A method for forming a thin-film resistor includes forming two insulators on the thin-film resistor, forming contact holes by performing wet etching processes, and forming interconnect and contact plugs at the same time. The invention also provides another method for forming a thin-film resistor that forms a thin-film resistor over the passivation layer instead. That is, forming a thin-film resistor on the top of the device, so that the resistance can be re-modified according to the actual needs.

Abstract: A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.

Abstract: A method of manufacturing a flash memory having a dual floating gate structure. A source/drain region is formed in a substrate. A first conductive layer is formed on the substrate and between the source/drain region. A first dielectric layer is located between the substrate and the first conductive layer. A floating gate mask is formed on the substrate and the first conductive layer to expose a portion of the first conductive layer. The portion of the first conductive layer and a portion of the first dielectric layer beneath the exposed conductive layer are removed. The floating gate mask is removed. A conformal second dielectric layer and a second conductive layer are formed over the substrate in sequence. The second conductive layer and the second dielectric layer are formed to respectively form a control gate and a third dielectric layer.

Abstract: A method of manufacturing copper interconnects includes the steps of first providing a semiconductor substrate having a dielectric layer thereon. The dielectric layer further includes a copper layer embedded within. An inter-metal dielectric layer is deposited over the dielectric layer. A via opening and a trench opening that exposes a portion of the copper layer are formed in the inter-metal dielectric layer. A thin barrier layer is formed over the exposed copper layer at the bottom of the via opening. The bottom part of the via opening is bombarded by atoms until the copper layer is exposed. Copper material is deposited to fill the via opening and the trench opening, thereby forming a damascene structure.

Abstract: A method for manufacturing a bit line and a bit line contact. A semiconductor substrate having a word line thereon is provided. Oxide spacers are formed on the sidewalls of the word line. A dielectric layer that covers the word line is formed over the entire substrate. A cap layer is next formed over the dielectric layer. The cap layer and the dielectric layer are patterned to form a trench in the dielectric layer. Silicon nitride spacers are formed on the sidewalls of the trench. In the subsequent step, the dielectric layer is etched down the trench to form a contact window that exposes a portion of the substrate. Polysilicon material is deposited into the contact window to form a polysilicon plug, and then metal silicide material is deposited into the trench above the plug to form a metal silicide layer.

Abstract: A semiconductor memory device and a method for mending a failed memory cell by directly programming a fuse memory cell. Using a tester to program the fuse memory cell directly, a laser machine is not required. In addition, to move the wafer for fuse allocation is not required either, so that the consumption in time and cost can be greatly reduced. Even after the package is complete, the repairing work can still be performed. In addition, whether the voltage source is connected or disconnected, the failed address information is kept and stored without being lost. A self-repair for self-test can thus be applied.

Abstract: A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.

Abstract: A fabrication method for an ultra short channel device comprising a self-aligned landing pad is described in which a first opening is formed in the oxide layer to define a gate structure region. A pad oxide layer is then formed in the first opening covering the substrate followed by forming a spacer on the inner sidewall of the first opening. Using the spacer as an etching mask, a portion of the oxide layer is removed to form a second opening exposing the substrate. A gate oxide layer is then deposited in the second opening, followed by forming a first conductive layer to fill the second opening. A third opening is then formed in the oxide layer to expose the substrate and to define the source/drain region. An ion implantation is then conducted in the substrate of the third opening to form a heavily doped region of the source/drain region. Thereafter, a landing pad is formed to fill the third opening and to electrically connect with the source/drain region.