Patents Represented by Attorney Charles W. Peterson, Jr.

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  • SRAM and dual single ended bit sense for an SRAM
    Patent number: 7170799
    Abstract: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Timothy J. Charest, Rajiv V. Joshi, Antonio Pelella
  • Processor with low overhead predictive supply voltage gating for leakage power reduction
    Patent number: 7134028
    Abstract: An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: November 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, David M. Brooks, Peter W. Cook, Philip G. Emma, Michael K. Gschwind, Stanley E. Schuster, Vijayalakshmi Srinivasan
  • Reprogrammable integrated circuit (IC) with overwritable nonvolatile storage
    Patent number: 7123517
    Abstract: A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has a number of selectable reference levels corresponding to reprogrammed cell threshold voltages. With each write cycle the nonvolatile storage cells are overwritten and then, compared against a different, e.g., higher, selectable reference level.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: October 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Matthew Breitwisch, Chung H. Lam, Steven Mittl, Jian W. Zhu
  • Backplane assembly with board to board optical interconnections
    Patent number: 7120327
    Abstract: An electronic system with components communicating over optical channels, a board initialization and continuity check and a method of transferring data over the optical channels. The system include a backplane with board to board signal wiring and a shared optical bus. Optical gratings are attached to the backplane and to circuit boards to pass optical energy between an optical transceiver and board/backplane. An optical transceiver at each end of each optical jumper relays optical signals between the optical jumpers and the connected circuit board or the backplane. Optical jumpers optically connect the circuit boards to the backplane.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: October 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ferenc M. Bozso, Philip G. Emma
  • Single supply level converter
    Patent number: 7119578
    Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: October 10, 2006
    Assignee: International Business Machines Corp.
    Inventors: Anthony Correale, Jr., Rajiv V. Joshi, David S. Kung, Zhigang Pan, Ruchir Puri
  • Seedless wirebond pad plating
    Patent number: 7115997
    Abstract: An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: October 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekhar Narayan, Kevin Shawn Petrarca
  • Multiple voltage integrated circuit and design method therefor
    Patent number: 7111266
    Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: September 19, 2006
    Assignee: International Business Machines Corp.
    Inventors: Anthony Correale, Jr., David S. Kung, Douglass T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach
  • Autonomic fiducial search pattern in an automated tape library
    Patent number: 7107121
    Abstract: A storage system or subsystem, method of locating components in the storage system and program product therefor. Storage system components have fiducial marks identifying component location. A sensor is located at an expected fiducial location and a first pass search for the fiducial is conducted along a search path. A second pass search, if needed, begins at a position located, horizontally, between the first pass start position and the system accessor home location.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 12, 2006
    Assignee: International Business Machines Corp.
    Inventors: James Arthur Fisher, Nicholas James Pakidis, Kerri Renee Shotwell
  • System and method for downloading a virus-free file certificate from a file server
    Patent number: 7099916
    Abstract: The present invention relates to computer viruses and more particularly to a method and system for requesting a virus-free certificate associated with a file of a file server and downloading this virus-free file certificate or a file including this virus-free file certificate from the file server. The method, for use in a client system (100), comprises the steps of: sending (401) a request to a file server for a virus-free certificate associated with a file to download from the file server, the request comprising one or a plurality of requirements (301 . . . 307) for the virus-free certificate; downloading (403) the file and the associated virus-free certificate, the virus-free certificate comprising a file signature (207) for certifying that the file is declared virus-free by a virus-free certificate authority (102).
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventors: Oliver Hericourt, Jean Francois Le Pennec
  • Optically connectable circuit board with optical component(s) mounted thereon
    Patent number: 7095620
    Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 22, 2006
    Assignee: International Business Machines Corp.
    Inventors: Ferenc M. Bozso, Philip G. Emma
  • Dual gate FinFet
    Patent number: 7091566
    Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corp.
    Inventors: Huilong Zhu, Jochen Beintner, Bruce B. Doris, Ying Zhang
  • SRAM with dynamically asymmetric cell
    Patent number: 7092280
    Abstract: A CMOS static random access memory (SRAM) array with dynamically asymmetric cells, an integrated circuit (IC) chip including the SRAM and a method of accessing data in the SRAM. Each column of cells is connected to a pair of column supply lines supplying power to the column. During each SRAM access, a higher voltage is applied to one column supply line in each pair of the columns being accessed to unbalance cells in the columns being accessed. Unbalanced cells become asymmetric during accesses and the supply imbalance favors the data state being written/read.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corp.
    Inventor: Rajiv V. Joshi
  • Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
    Patent number: 7093206
    Abstract: A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corp.
    Inventors: Minakshisundaran B. Anand, Matthew S. Angyal, Alina Deutsch, Ibrahim M. Elfadel, Gerard V. Kopcsay, Barry J. Rubin, Howard H. Smith
  • Dual function FinFET, finmemory and method of manufacture
    Patent number: 7087952
    Abstract: A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Bruce B. Doris, Jochen Beintner
  • Method and program product of level converter optimization
    Patent number: 7089510
    Abstract: A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corp.
    Inventors: Anthony Correale, Jr., David S. Kung, Douglass T. Lamb, Zhigang Pan, Ruchir Puri
  • Integrated circuit logic with self compensating block delays
    Patent number: 7084476
    Abstract: An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corp.
    Inventors: Puneet Gupta, Fook-Luen Heng, David S. Kung, Daniel L. Ostapko
  • Synchronous pipeline with normally transparent pipeline stages
    Patent number: 7076682
    Abstract: A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a local clock gating a corresponding stage. The input and output stages are normally opaque and intermediate stages are normally transparent. Data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: July 11, 2006
    Assignee: International Business Machines Corp.
    Inventor: Hans M. Jacobson
  • Processor with demand-driven clock throttling power reduction
    Patent number: 7076681
    Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: July 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Daniel M. Citron, Peter W. Cook, Philip G. Emma, Hans M. Jacobson, Prabhakar N. Kudva, Stanley E. Schuster, Jude A. Rivers, Victor V. Zyuban
  • Interlocked synchronous pipeline clock gating
    Patent number: 7065665
    Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: June 20, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hans M. Jacobson, Prabhakar N. Kudva, Pradip Bose, Peter W. Cook, Stanley E. Schuster
  • Field emission phase change diode memory
    Patent number: 7057923
    Abstract: A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: June 6, 2006
    Assignee: International Buisness Machines Corp.
    Inventors: Stephen S. Furkay, David V. Horak, Chung H. Lam, Hon-Sum P. Wong