Abstract: An apparatus configured to interface a first clock speed of a multiqueue storage device and a second clock speed of an interface. The apparatus may be configured to control a flow of variable size data packets.

Abstract: A video decoder for decoding video pictures encoded according to the MPEG-2 standard, having reduced memory requirements, including a memory for storing means for storing a plurality of anchor frames, the decoder employing such anchor frames to generate B-frames, and including block-to-raster buffer means for holding B-frame data for display, the decoder being operable in first and second modes of operation, wherein in a first mode of operation a picture is encoded as a single frame and the video decoder decodes the entire frame twice wherein in a first decoding a set of lines of a first field are provided to the buffer for display, whereas in a second decoding lines from a second field are provided to the buffer for display; and wherein in a second mode of operation in which two consecutive field pictures of a frame are decoded, a first field picture is decoded and provided to the buffer means for display, and then a second field picture is decoded and provided to the buffer means for display.

Abstract: An apparatus comprising a Darlington transistor pair and a common-base transistor. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The common-base transistor may be coupled between an output transistor of the Darlington transistor pair and the output node. The common-base transistor may have a base configured to receive a reference voltage.

Abstract: An apparatus comprising a synchronous circuit configured to (i) shift a JTAG instruction signal in response to a first control signal, (ii) decode the JTAG instruction signal while the JTAG instruction signal is shifted and (iii) latch the decoded JTAG instruction signal in response to a second control signal.

Abstract: A circuit for reducing the number of bits in a K bit value from K to N bits. The circuit generally comprises a first summing circuit, a control circuit, an error feedback circuit, a second summing circuit, and a processor. The first summing circuit may add an error offset value and the N+m MSB's of the K bit value to produce a result data value. The control circuit may generate a dither offset value. The error feedback circuit may receive m LSBs of the result data value and generate an error value in dependence on the m LSBs. The second summing circuit may add the dither offset value and the error value to provide the error offset value. The processor may selectively control generation of the dither offset value and the error value.

Abstract: A circuit generally comprising an interface circuit and an arbitration circuit is disclosed. The interface circuit may be couplable between a peripheral device and a plurality of ports. The arbitration circuit may be coupled to the interface circuit. The arbitration circuit may be configured to (i) store a plurality of associations between a plurality of time slots and the ports, (ii) check the associations in a subset comprising at least two of the time slots in response to receiving an arbitration request from a first requesting port of the ports, and (iii) generate a grant for the first requesting port to communicate with the peripheral device in response to the first requesting port matching at least one of the associations in the subset.

Abstract: An apparatus comprising a transmit data path, a receive data path, a first circuit and a second circuit. The first circuit may be configured to transfer data between a first interface and the transmit and receive data paths. The second circuit may be configured (i) to transfer the data between the transmit and receive data paths and a second interface and (ii) to control a configuration update of the first and second circuits in response to a plurality of control signals. The configuration of the first and second circuits is generally dynamically updated.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: An apparatus comprising a polarity switch. The polarity switch may comprise a number of transmission gates. An output of the polarity switch may selectably present either (i) a signal that varies in response to a control signal or (ii) a predetermined logic level that is independent of the control signal.

Abstract: An apparatus comprising a memory device and one or more control circuits. The memory device may be configured to store and retrieve data. The one or more control circuits may be configured to control access to the memory device. Each of the control circuits may be configured to provide a readback of an internal address value when in a first state and a readback of a mask value when in a second state.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of intermediate signals from a data signal. Each of the intermediate signals may be switchable between (i) a common delay and (ii) one of a plurality of different staggered delays determined by a stagger signal. The a second circuit may be configured to generate a plurality of first drive signals by gating the intermediate signals with a plurality of enable signals. The a third circuit may be configured to generate a plurality of first output signals at a transmit interface of a chip by buffering the first drive signals.

Abstract: A system for controlling arbitration that may be used for a bus. The system generally comprises a bus, at least one master, and a first circuit coupled between the bus an the at least one master. The at least one master may be configured to present at least one transfer signal. The first circuit may be configured to (i) grant a bus mastership to a first master of the at least one master, (ii) present a first transfer signal of the at least one transfer signal to the bus in response to granting the bus mastership to the first master, (iii) remove the bus mastership from all masters of the at least one master, and (iv) present an idle transfer signal to the bus in response to removing the bus mastership from all masters.

Abstract: A circuit that may be configured to detect a lockout condition of a phase lock loop (PLL) circuit. The circuit may be configured to forcibly correct an operating frequency of the PLL circuit.

Abstract: An apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state signal in response to an address signal and a counter control signal. The generation circuit may (i) comprise an internal counter register and (ii) be configured to generate an output address in response to the mask signal, the unique counter control signal, and the incremented state signal. The mask signal may be configured to selectively mask the internal counter register.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to arbitrate a plurality of input request signals and present one or more first control signals. The second circuit may be configured to control the arbitration in response to an adjustable balance point of the input request signals, where the balance point is adjusted to reduce a metastable state of the first circuit.

Abstract: An apparatus (22) for reducing noise in a tracking error signal receives input signals from an array (5) of photodetectors, each input signal indicating the amount of laser light incident on the corresponding photodetector reflected from an optical disc. The input signals from diagonal pairs of photodetectors are summed and then filtered and digitized to produce a pair of digital input signals. A signal difference generator (20) produces first and second difference signals when either the first or the second digital input signals are received. The first and second difference signals are received by a programmable timing element having a user programmable device (41) and a signal limiting device (32, 33, 34, 35) for limiting the duration of the first or second difference signals provided at respective first or second outputs of the programmable timing element to a user programmable maximum value.

Abstract: A switch for at least two clock domains, comprising (a) first and second synchronizers in a first clock domain, (b) third and fourth synchronizers in a second clock domain, and (c) a state machine configured to interface with said synchronizers, thereby controlling switching between said first and second clock domains.

Abstract: An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals.

Abstract: One aspect of the invention comprises an apparatus comprising a frame for transmitting information via a network, comprising one or more packets of different data types and lengths located anywhere inside the frame. Another aspect of the present invention comprises a network configured to transfer a plurality of frames and one or more nodes coupled to the network. Each of the one or more nodes may be configured to receive and/or transmit one or more of the plurality of frames. Each of the plurality of frames may be configured to store one of a number of packets of different data types and different data lengths, anywhere within the frame.

Abstract: A method for determining the capacitance of an analog/mixed signal circuit, comprising the steps of (A) acquiring a capacitance at a plurality of different input slope rates, (B) verifying each acquired capacitance, (C) determining an average capacitance of said plurality of different input slope rates over a partial average range and (D) determining an accuracy of the capacitance.