Patents Represented by Attorney Christopher P. Maiorana P

Find this attorney in the Justia Lawyer Directory

  • Read/modify/write registers
    Patent number: 6901490
    Abstract: The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be configured to access a selected one of the registers. The logic circuit may be coupled to the plurality of multi-bit registers and responsive to data received through the interface for selectively writing a predetermined logic state to at least one first bit of the selected register while leaving at least one second bit in the selected register with an unmodified state.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: May 31, 2005
    Assignee: LSI Logic Corporation
    Inventor: Ray Brown
  • Minimum latency propagation of variable pulse width signals across clock domains with variable frequencies
    Patent number: 6901528
    Abstract: An apparatus comprising a counter circuit, a first register circuit, a second register circuit and an output circuit. The counter circuit may be configured to generate a count signal in response to a data input signal and a first clock signal operating in a first clock domain. The first register circuit may be configured to generate a first control signal in response to the count signal. The second register circuit may be configured to generate a second control signal in response to the data input signal. The output circuit may be configured to generate a data output signal operating in a second clock domain in response to the first control signal, the second control signal, the count signal, and a second clock signal.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: May 31, 2005
    Assignee: LSI Logic Corporation
    Inventor: Kasturiranga Rangam
  • DSP memory bank rotation
    Patent number: 6895488
    Abstract: An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: May 17, 2005
    Assignee: LSI Logic Corporation
    Inventors: Ho-Ming Leung, Wern-Yan Koe, Fan Zhang, Kasturiranga N. Rangam, Venkatesh Balasubramanian
  • Central dynamic memory manager
    Patent number: 6883082
    Abstract: A circuit generally comprising a memory and a core module is disclosed. The memory may be configured as (i) a first stack having a plurality of index pointers and (ii) a table having a plurality of entries. The core module may be configured to (i) pop a first index pointer of the index pointers from the first stack in response to receiving a first command generated by a first module external to the circuit, (ii) assign a first entry of the entries identified by the first index pointer to the first module, (iii) generate an address in response to converting the first index pointer and (iv) transfer the address to the first module.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: April 19, 2005
    Assignee: LSI Logic Corporation
    Inventors: Qasim R. Shami, Jagmohan Rajpal
  • Jtag test access port controller used to control input/output pad functionality
    Patent number: 6851079
    Abstract: A circuit that may be used to implement boundary scan testing. The circuit generally comprises a pad circuit, a core logic, a cell, and a test circuit. The pad circuit may be configured to transfer a data signal in response to a pad control signal. The core logic may be configured to (i) exchange the data signal with the pad circuit and (ii) present a control signal. The cell may be configured to (i) transfer the data signal between the pad circuit and the core logic and (ii) swap the data signal and a test signal. The test circuit may-be configured to (i) exchange the test data signal with the cell, (ii) store a test control signal, and (iii) multiplex the test control signal and the control signal to present the pad control signal.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: February 1, 2005
    Assignee: LSI Logic Corporation
    Inventor: Michael A. Hergott
  • SRAM self-timed write stress test mode
    Patent number: 6850075
    Abstract: An integrated circuit includes a test circuit that may be configured to generate a test signal having a predetermined pulse width in response to a control input. The test signal may track process corners of the integrated circuit and may be used to predict a failure of the integrated circuit.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: February 1, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Colin Davidson, John Niven
  • Method and/or apparatus to sort request commands for SCSI multi-command packets
    Patent number: 6842792
    Abstract: An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: January 11, 2005
    Assignee: LSI Logic Corporation
    Inventors: Stephen B. Johnson, Bradley D. Besmer, Guy W. Kendall, Christopher J. McCarty, Andrew C. Brown
  • Speed power efficient USB method
    Patent number: 6839778
    Abstract: An apparatus comprising a peripheral device and a host device. The peripheral device may be connected to the host device. The speed of the peripheral device may be adjusted in response to one or more predetermined conditions.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: January 4, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Ronald H. Sartore, Steven P. Larky, Cathal G. Phelan
  • Data processing system
    Patent number: 6831654
    Abstract: A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in the form of a linked list comprising a plurality of items of control data. The register may be associated with the block move engine and configured to control the block move engine, in response to the control data. The reader may be configured to read the control data from the memory and apply the control data to the register.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: December 14, 2004
    Assignee: LSI Logic Corporation
    Inventors: David Neil Pether, Stephen John Gibbon
  • Diagnostic architecture using FPGA core in system on a chip design
    Patent number: 6829751
    Abstract: A system for designing an integrated circuit (IC). The system generally comprising a circuit and a programmable portion used for diagnostics and finding bugs. The circuit generally comprises (i) a functional portion and (ii) a logic portion that may be connected to the functional portion. The logic portion generally includes one or more interfaces. The programmable portion may be configured to detect, correct and/or diagnose errors in the logic portion through the one or more interfaces.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: December 7, 2004
    Assignee: LSI Logic Corporation
    Inventors: Zhaohui Shen, Daniel Watkins
  • Method and apparatus for the use of discriminators for priority arbitration
    Patent number: 6826642
    Abstract: An apparatus comprising a margin logic circuit, one or more discriminator circuits and a sense circuit. The margin logic circuit may be configured to receive a plurality of requests and present one or more control signals. The one or more discriminators may be configured to (i) present one or more leading access signals and (ii) receive the one or more control signals and the plurality of requests. The sense circuit may be configured to receive the one or more leading access signals and the plurality of requests and present grant access signal. The sense circuit may be configured to reduce the effects of metastable conditions.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: November 30, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventor: Grahame K. Reynolds
  • Method for circuit recovery from overstress conditions
    Patent number: 6819539
    Abstract: A method for circuit recovery from overstress conditions, comprising the steps of (A) detecting an event and (B) resetting a device when the event is a first predetermined type and providing recovery when the event is a second predetermined type.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: November 16, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: David G. Wright, Timothy J. Williams
  • Method and architecture to associate enclosure service data with physical devices on a fibre channel loop with soft addresses
    Patent number: 6820139
    Abstract: An apparatus comprising one or more drive portions and a controller. The one or more drive portions may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to the one or more drives.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: November 16, 2004
    Assignee: LSI Logic Corporation
    Inventors: Charles Binford, Ruth Hirt, Lance Lesslie
  • Push/pull multiplexer bit
    Patent number: 6815984
    Abstract: An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: November 9, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Benjamin J. Bowers, Brian P. Evans, Jeffery Scott Hunt
  • System and method for reducing power consumption in a universal serial bus device
    Patent number: 6816976
    Abstract: The present invention concerns a method for reducing power consumption in a device, comprising the steps of (A) receiving one or more packets, (B) determining a type of each of the one or more packets and (C) suspending, waking, or partially waking the device in response to a particular type of packet.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: November 9, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: David G. Wright, Timothy J. Williams
  • Logic for providing arbitration for synchronous dual-port memory
    Patent number: 6816955
    Abstract: An apparatus for providing arbitration for a dual-port memory. The apparatus may be configured to prevent a write cycle extension during contention between simultaneous read and write operations.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: November 9, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul
  • Configurable fast clock detection logic with programmable resolution
    Patent number: 6816979
    Abstract: An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: November 9, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jiann-Cheng Chen, Somnath Paul, S. Babar Raza
  • Raid volume for sequential use that needs no redundancy pre-initialization
    Patent number: 6813687
    Abstract: A method for providing sequential initialization of redundancy data in a volume comprising the steps of: (A) defining a boundary; (B) determining a location of the data with respect to the boundary; and (C) initializing a redundancy location of the volume and writing the data and a redundancy of the data to the volume.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: November 2, 2004
    Assignee: LSI Logic Corporation
    Inventor: Donald R. Humlicek
  • Address counter test mode for memory device
    Patent number: 6813741
    Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: November 2, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: George M. Ansel, David R. Lindley, Jeffrey W. Gossett, Junfei Fan, Andrew L. Hawkins, Michael D. Carlson
  • EMC enhancement for differential devices
    Patent number: 6813672
    Abstract: An apparatus configured to communicate through a differential bus to a device. The apparatus may be configured to disconnect and reconnect the device in response to an abnormal reset event to provide enhanced electromagnetic compliance (EMC).
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: November 2, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Bijan Kamran, Warren S. Snyder