Abstract: An apparatus generally comprising a plurality of processors, a trace circuit, and a connector circuit. The trace circuit may be configured to present information at a port for debugging software in a selected processor of the processors. The connector circuit may be configured to (i) couple the trace circuit to the selected processor in response to a select signal and (ii) transfer the information from the selected processor to the trace circuit while the selected processor is executing the software.

Abstract: An apparatus for receiving and processing an electrical signal in the form of a pulse train comprising a plurality of pulses. The apparatus generally comprises a processor, a memory and a timer. The timer may be configured to generate a respective value representative of the positions of each leading and trailing edge of each pulse in the pulse train. The memory may be configured to receive the value and write the value. The timer may be configured to generate an interrupt signal following receipt of the trailing edge of the last pulse in the pulse train and apply the interrupt signal to the processor. The processor may read the values stored in the memory for decoding the pulse train in response to said interrupt signal.

Abstract: A method for resource notification is disclosed. The method generally comprises the steps of (A) buffering a plurality of messages received from a plurality of busses, (B) arbitrating among the messages, (C) writing the messages in response to the arbitration, and (D) generating a plurality of notification signals on a plurality of lines in response to the messages as written to a plurality of addresses.

Abstract: A method for providing orderly service delivery to clients over a network, comprising the steps of (A) requesting data from a location and (B) if a denial is received, notifying a particular client of availability.

Abstract: A semiconductor comprising a plurality of first building blocks arranged in one or more first rows and a plurality of second building blocks arranged in one or more second rows. The one or more second rows are interleaved with the one or more first rows and the first building blocks and the second building blocks each provide a segment of horizontal and a segment of vertical routing.

Abstract: An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

Abstract: An apparatus comprising a plurality of first circuits and a second circuit. Each of the first circuits may be configured to translate attributes and data between one of a plurality of first predetermined formats and a second predetermined format. The second circuit may be configured to route the attributes and data in the second predetermined format from one of the first circuits to another of the first circuits.

Abstract: An apparatus comprising a processor and a translator circuit. The processor may (i) comprise a number of internal registers and (ii) be configured to manipulate contents of the internal registers in response to instruction codes of a first instruction set. The translator circuit may be configured to implement a stack using one or more of the internal registers of the processor.

Abstract: A circuit for use in a data packet transmission system. The circuit generally comprises a buffer and a test circuit. The buffer may be configured to store a plurality of data packets. The test circuit may be configured to (i) monitor a number of the plurality of data packets in the buffer, (ii) permit an additional data packet to the plurality of data packets into the buffer responsive to the number being less than a first threshold, and (iii) discard the additional data packet in accordance with a probabilistic test responsive to the number being greater than the first threshold.

Abstract: A method is provided for encoding K>1 sequentially presented video pictures. Each of the K pictures is divided into an m>1 row×n>1 column array of non-overlapping coding units of equal sizes. Each coding unit occupies a respective coding unit position in the picture from which it was divided. An arbitrary, pseudo random pattern of coding units is selected for refreshing during each of the K pictures. Each pattern selected during any given one of the K pictures includes a sequence of one or more coding units of the array. In addition, the pixels of each coding unit selected for refreshing during a kth picture occupy different pixel positions than each coding unit selected for refreshing during a preceding one of the 1st to (k?1)th pictures of the K pictures. Furthermore, each pixel position of a moving picture image formed from the K pictures is selected for refreshing once over the sequence of K pictures.

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to (i) measure a width of a symbol in the input signal in response to the plurality of samples and the plurality of phases of the reference clock and (ii) adjust the measured width in response to a correction signal.

Abstract: A method for data verification in a data storage environment including the steps of (A) sending a command from an initiator to a target, where the command defines an expected data pattern, (B) sending a block write command from the initiator to the target, where the write command initiates sending data from the initiator to the target, (C) comparing data received to the expected data pattern and (D) generating a status indication in response to the comparison.

Abstract: An integrated circuit comprising a plurality of link layer controllers. The plurality of link layer controllers may be configured to operate independently in a first mode and cooperatively in a second mode.

Abstract: A circuit generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals each representative of the state of the input signal during a plurality of clock cycles. The second circuit may be configured to present a filtered signal in response to a selected number of the intermediate signals having a predetermined state.

Abstract: An apparatus comprising a data modification circuit and a composite circuit. The data modification circuit may be configured to generate a first output data stream in response to a first one or more of the data streams. The composite circuit may be configured to generate a combined output data stream in response to the first output data stream and remaining data streams.

Abstract: An apparatus comprising an analog circuit, a first digital circuit, and a second digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The first digital circuit may be configured to generate (i) one or more data signals, (ii) a first strobe signal, and (iii) a second strobe signal in response to the plurality of samples, the plurality of phases, and a correction signal. The second digital circuit may be configured to generate the correction signal and a width signal in response to (i) the one or more data signals, (ii) the first strobe signal, and (iii) the second strobe signal.

Abstract: The present invention is a method for operating a computer-based accounts payable system. The user inputs a bill that includes a billing code. The system then determines whether the billing code is present in the budget database. If the billing code is present in the budget database, the system approves payment of an amount associated with the billing code in the budget database. If the billing code is not present in the budget database, the system approves payment of a budget amount associated with the billing code in a default budget database. In the preferred embodiment, the system also checks whether a particular task has been completed before approving payment of said bill, and checks to insure that a previous bill covering the same task has not been paid previously.

Abstract: A system generally having a first circuit, a second circuit, and a pair of non-crossing conductive paths. The first circuit may be configured to convert between (i) a serial signal on a first differential interface and (ii) a parallel signal. The pair of non-crossing conductive paths may connect the first differential interface with a second differential interface. The second circuit may be configured to invert the parallel signal in response to a control signal in an inverting state.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first portion of an output data stream in response to a first portion of an input data stream. The second circuit may be configured to present a second portion of the output data stream in response to a second portion of the input data stream. The apparatus may be configured to perform color and gamma correction on the input data stream to generate the output data stream in response to one or more control signals. In one example, the apparatus may comprise block move engine (BME).

Abstract: A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.