Patents Represented by Attorney Christopher P. Maiorana P

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  • High-speed, low-power crossbar switch
    Patent number: 6965299
    Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: November 15, 2005
    Assignee: LSI Logic Corporation
    Inventors: William J. Dally, Daniel K. Hartman
  • High speed network protocol stack in silicon
    Patent number: 6959007
    Abstract: An apparatus comprising a media access controller (MAC), a configurable packet switch, and a network protocol stack in silicon. The network protocol stack may be configured to couple the media access controller to the configurable packet switch.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: October 25, 2005
    Assignee: LSI Logic Corporation
    Inventors: Danny C. Vogel, Clinton P. Seeman
  • Method of detecting internal frame skips by MPEG video decoders
    Patent number: 6952452
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate a random number signal, (ii) read a data signal, and (iii) generate one or more control signals. The second circuit may be configured to (i) store the random number signal, (ii) receive and store a decoded video signal, and (iii) present the data signal. The first circuit may be further configured to compare the data signal with the random number signal and (i) when the data signal matches the random number signal generate a first of the control signals and (ii) when the data signal fails to match the random number signal generate a second of the control signals.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 4, 2005
    Assignee: LSI Logic Corporation
    Inventors: Brett J. Grandbois, Gareth D. Trevers
  • Linearized digital phase-locked loop method
    Patent number: 6950484
    Abstract: A method for synchronizing a clock signal to a data signal, comprising the steps of (A) detecting an edge of the data signal, (B) determining whether a position of the edge is within a zone and (B) if the edge is not within the zone, adjusting the clock signal towards the position of the edge.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 27, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Timothy D. Jordan, Terry D. Little, Kamal Dalmia
  • Low power, variable precision DDA for 3D graphics applications
    Patent number: 6947056
    Abstract: An apparatus generally having a register, an adder circuit and a mask circuit is disclosed. The register may be configured to replace a current value with a new value in response to a clock value. The adder circuit may be configured to generate the new value by adding the current value to a delta value. The mask circuit may be configured to mask at least one value among the delta value, the new value and the clock value in response to a mask value having a plurality of bits.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventor: Mark J. Kwong
  • Multi-resolution Viterbi decoding technique
    Patent number: 6948114
    Abstract: A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics. A third step replaces the selected subset of first precision state metrics with the second precision state metrics. A fourth step stores the first precision state metrics and the second precision state metrics.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
  • Adaptive noise cancellation (ANC) for DVD systems
    Patent number: 6940982
    Abstract: An apparatus comprising an input, a noise cancellation circuit, an audio circuit and a mixing circuit. The input may be configured to receive one or more input signals. The noise cancellation circuit may be configured to generate a first processed audio signal having reduced noise in response to the input signals. The audio circuit may be configured to generate a second audio signal from a digital source. The mixing circuit may mix the processed audio signal and the second audio signals to generate an output signal.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventor: Daniel Watkins
  • Video decoding during I-frame decode at resolution change
    Patent number: 6940909
    Abstract: A method of buffering a video signal is disclosed. The method generally includes the steps of (A) storing a plurality of pictures decoded from the video signal having a first resolution in a memory space divided into a plurality of first buffers each having a first size, (B) dividing the memory space into a plurality of second buffers each having a second size in response to the pictures in the video signal changing to a second resolution, and (C) converting at least one unavailable buffer of the second buffers to an available condition by marking at least one unread picture of the pictures from the memory space as destroyed.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventor: Elliot N. Linzer
  • Generator of graphics in computer system
    Patent number: 6930688
    Abstract: An apparatus for generating graphics is connectable in a computer system between a system processor and a system memory by way of a data bus. The apparatus comprises two registers for the storage of X and Y coordinates respectively of a single pixel. The coordinates are applied to an address conversion calculation unit for calculating a linear memory address corresponding to the pixel coordinates and the data representative of the pixel is stored in the system memory at the calculated address. The two registers are memory mapped to appear at two or more locations in memory such that operation of the apparatus is dependent on the memory location used by each register. The apparatus carries out many of the repetitive operations required in the generation of graphics.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: August 16, 2005
    Assignee: LSI Logic Corporation
    Inventors: David Neil Pether, Stephen John Gibbon
  • Programmable transmit SCSI equalization
    Patent number: 6931560
    Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: August 16, 2005
    Assignee: LSI Logic Corporation
    Inventors: Edson W. Porter, Brian E. Burdick, Todd A. Randazzo, Kevin J. Bruno, Stephen R. Burnham, William K. Petty
  • Context based adaptive binary arithmetic CODEC architecture for high quality video compression and decompression
    Patent number: 6927710
    Abstract: A method for compressing/decompressing data, comprising the steps of translating a first representation of data to a second representation of the data and translating the second representation of the data to a third representation of the data.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: August 9, 2005
    Assignee: LSI Logic Corporation
    Inventors: Elliot N. Linzer, Ho-Ming Leung
  • Filter for disk drive bi-phase servo demodulation
    Patent number: 6927932
    Abstract: An apparatus comprising a sampler circuit and a filter circuit. The sampler circuit may be configured to generate a digital signal in response to a pre-amplified signal. The filter circuit may be configured to generate a track ID signal in response to the digital signal. The filter circuit may also be configured to (i) improve or increase signal-to-noise ratio (SNR) and (ii) reject DC offset errors.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: August 9, 2005
    Assignee: LSI Logic Corporation
    Inventors: David L. Schell, Kevin G. Christian
  • Automatic translation from SCSI command protocol to ATA command protocol
    Patent number: 6925519
    Abstract: A device generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) communicate with a host via a first bus (ii) using a small computer system interface (SCSI) protocol having a plurality of command descriptor blocks. The second circuit configured to (i) communicate with a remote device with a via a second bus, (ii) using an advanced technology attachment (ATA) protocol and (iii) translate a subset of the command descriptor blocks to the ATA protocol in application specific hardware.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: August 2, 2005
    Assignee: LSI Logic Corporation
    Inventors: Brian A. Day, Timothy E. Hoglund, Ganesan Viswanathan, Ayyavu Vetrivel
  • Method of protecting high definition video signal
    Patent number: 6925181
    Abstract: A system controls reproduction of a video transmission between a transmitter and a receiver. The system includes an encryptor with an offset generator adapted to receive the encrypted frame key and to generate a sequence of pseudo-random values for the color component; and an adder coupled to the offset generator and to the color component signal for providing an encoded color component signal. The system also includes a decryptor with a decryptor offset generator adapted to receive the encrypted frame key and to generate a decryptor pseudo-random value for the color component; and a subtractor coupled to the offset generator and to the color component signal for subtracting the offset signal from the color component signal.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: August 2, 2005
    Assignee: LSI Logic Corporation
    Inventors: Leslie Kohn, David A. Barr, Didier Le Gall
  • Method for creating derivative integrated circuit layouts for related products
    Patent number: 6922823
    Abstract: A method for creating a derivative semiconductor design layout is disclosed. The method generally comprises the steps of (A) receiving a plurality of changes from a user for a first layout of a semiconductor design having a plurality of first layers, (B) storing the changes in a plurality of second layers and (C) displaying the derivative semiconductor design layout to the user in response to logically operating on the first layers and the second layers.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: July 26, 2005
    Assignee: LSI Logic Corporation
    Inventor: David P. Tester
  • Time sharing a single port memory among a plurality of ports
    Patent number: 6920510
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: July 19, 2005
    Assignee: LSI Logic Corporation
    Inventors: Gary Chang, Hong-men Su
  • Video decoder and encoder transcoder to and from re-orderable format
    Patent number: 6917310
    Abstract: A method for decoding an input bitstream is disclosed. The method generally includes the steps of (A) generating an intermediate bitstream having an intermediate encoded format by converting the input bitstream having an input encoded format and an input order, (B) storing the intermediate bitstream in the input order and (C) generating an output signal having an output order by decoding the intermediate bitstream.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: July 12, 2005
    Assignee: LSI Logic Corporation
    Inventors: Eric C. Pearson, Elliot N. Linzer, Lowell L. Winger
  • Logic built-in self test (BIST)
    Patent number: 6904554
    Abstract: An apparatus comprising a plurality of flip-flops each comprising (i) a first input, (ii) a second input and (iii) an output, where (a) each of the outputs are coupled to the first input of a subsequent flip-flop to form a chain, (b) the first input of a first of the flip-flops receives a pattern signal, (c) each of the second inputs receives a respective first logic signal, and (d) each of the outputs presents a respective second logic signal in response to the signals received at the first and second inputs, a pattern generator configured to generate the pattern signal, and a checking circuit configured to generate a check signal in response to the second logic signal of a last of the flip-flops. The pattern signal and the first logic signals are generally selected to influence a behavior of the apparatus.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: June 7, 2005
    Assignee: LSI Logic Corporation
    Inventors: Stefan G. Block, David R. Rueveni
  • Scan chain testing of integrated circuits with hard-cores
    Patent number: 6901544
    Abstract: The invention relates to an integrated circuit including a hard-core and a peripheral circuit. The hard-core and the peripheral circuit each include respective registers, which are couplable for scan chain testing by respective scan chain paths within the core and within the peripheral circuit. In order to avoid timing problems between the two scan chain paths, a lock-up latch is provided within the hard-core. The lock-up latch has an input coupled to the last register in the scan chain path within the hard-core, and an output coupled to the first register in the scan chain path in the peripheral circuit. The lock-up latch forms part of the hard-core and is clocked by the same clock signal as the last register in the hard-core scan chain path.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 31, 2005
    Assignee: LSI Logic Corporation
    Inventors: Joerg Huth, Andreas Hils
  • Proportional to temperature voltage generator
    Patent number: 6901022
    Abstract: A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: May 31, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventor: Timothy E. Fiscus