Abstract: A method and apparatus for driving a plurality of addressable elements consist of driving and selectively enabling one or more addressable elements arranged as an M×N array using two drivers. The columns may be addressed in parallel. Columns may be coupled to a conductor by a charge transfer/isolation circuit. A voltage waveform or pulse train may be propagated down the display conductor such that a pulse is present on the display conductor for each element of a row of elements to be addressed. When the beginning of the pulse train has propagated to the last column tap-off point so that a different pulse is present at each column tap-off point corresponding to the row of elements to be selected, a corresponding charge is transferred to each column conductor in parallel. Thus, a voltage is supplied to select each element on the selected row as determined by the state of the pulse train at each column tap-off point.

Abstract: A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The extended register file includes two dedicated registers and a plurality of general-use registers. The extended register file is mapped to a region in main memory. One dedicated register of the extended register file stores the physical base address of the memory region. Another dedicated register of the extended register file is used to store bits to indicate the status of the extended register file. A set of extended instructions is implemented for transferring data to and from the extended register file.

Abstract: A metallization structure and method for fabricating such a metallization structure are presented. The present method preferably includes forming a void within a metal layer. The void may have a void pressure level, which is preferably approximately equal to the pressure in a deposition chamber in which the metal layer is arranged when the void is formed. Subsequently, the void may be collapsed by increasing a pressure level outside of the void to a collapsing pressure level significantly above the void pressure level. Increasing a pressure level outside of the void preferably includes increasing a pressure level within the deposition chamber to a collapsing pressure sufficient to collapse the void. A metallization structure formed by such a process may be substantially void-free, even in narrow, high aspect ratio metallization cavities.

Abstract: A spinal plate system and method for fixation of the human spine is provided. In an embodiment, the system includes a bone plate, a bone screw and a ring. The bone screw preferably connects the bone plate to a bone, and the ring preferably fixes the bone screw into a borehole of the bone plate such that the bone screw extends from the bone plate at a selected angle. The ring is preferably capable of swiveling within the borehole to allow the bone screw to be angulated at a plurality of angles oblique to the plate. The bone screw may have a head having a tapered, threaded surface for engaging the ring. The ring preferably has threading on its inner surface for mating with the threading on the head. The inner surface of the ring may be tapered. Movement of the head through the ring preferably expands the ring against the bone plate to fix the bone screw at a selected angle relative to the bone plate.

Abstract: The present invention relates to a centralizer for use downhole in a well. The centralizer body has one or more contact arms attached to a movable collar. The body is run into the well to a selected depth within the well and the collar is moved to move the contact arms radially outwardly from the body. The collar can be moved sequentially with hydraulic fluid pressure to control the contact arm movement. The contact arm movement can also be locked to retain the centralizer radial force within the well.

Abstract: A reel assembly having three reels disposed side-by-side on a shaft pays out coiled tubing to an injector. A conveyor is used to support and guide the coiled tubing during travel from the reels to the injector. The conveyor is selectively rotatable such that the conveyor may be directed to the reel which actively pays out the coiled tubing. In another embodiment, two reels are slidably disposed side-by-side on a shaft. A conveyor is used to support and guide the coiled tubing during travel from the reels to the injector. In this embodiment, the conveyor is directed to a specific location on the shaft and the reels are slid into the specific location for coiled tubing payout.

Abstract: The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement included within the relative branch instruction is added to the address corresponding to the relative branch instruction, thereby generating the target address. The processor replaces the displacement field of the relative branch instruction with an encoding of the target address, and stores the modified relative branch instruction in the instruction cache. The branch prediction mechanism may select the target address from the displacement field of the relative branch instruction instead of performing an addition to generate the target address. In one embodiment, relative branch instructions having eight bit and 32-bit displacement fields are included in the instruction set executed by the processor.

Abstract: An apparatus and method that minimize the hardware and computation time needed to generate 64 bit addresses is described. To generate a 64 bit address, an address generation unit may need to add a 64 bit base value, a 64 bit index value, and a 32 bit displacement value to a 64 bit segment descriptor table address. The address generation unit can include a first adder and a second adder. The first adder can add a displacement to a first portion of the segment descriptor table address to generate an intermediate result. The intermediate result can be concatenated with a second portion of the segment descriptor table address and this concatenated result can be conveyed to the second adder. The second adder can add the concatenated result to a base value and an index value to generate a virtual address.

Abstract: A method for creating a frequency domain semblance for use in conjunction with acoustic logging tools is disclosed. Such a frequency domain semblance may be obtained by transforming an acoustic signal received at multiple depths into the frequency domain, combining the received waveforms corresponding to the different depth, and expressing the result in a graph with slowness and frequency axes. This graph shows the frequency-slowness location for the acoustic signal, as well as for other related signals that may inadvertently be generated by the acoustic logging tool. This information may then be used to more clearly measure the slowness of the received acoustic signal. Another aspect of the invention is the treatment of two or more time domain semblances as probability density functions of the slowness for an acoustic signal. This enables the combination of time domain semblances from the same depth in the wellbore.

Abstract: In a first aspect, the invention is a method for interfacing a generic program with the ASL code in an ACPI system. The method comprises storing information from a generic program in a shared memory; accessing the ASL code; and retrieving the stored information with the ASL code. In a second aspect, the invention is a method for testing ASL PnP code in an ACPI system. The method comprises identifying a configurable PnP device; disabling the identified configurable PnP device; testing the disabled, configurable PnP device for a configuration; and verifying that, for the tested configuration, the resulting current resources match the set resources. In variations of these aspects, the methods may be performed by instructions encoded on a computer-readable, program storage medium and used to program a computer.

Abstract: A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region.

Abstract: A method and apparatus is disclosed for transmitting data about an object within a defined field and using the transmitted data to generate a virtual object on the display screen of a computer. In one embodiment of the present invention the object used to transmit input data is a wireless glove assembly. The glove assembly supports a transmitting device which transmits data bursts, containing position and gesture information, in the radio frequency wavelength to four stationary receivers. The received signal is converted to a digital signal and input to a microprocessor control unit. The software used in the microprocessor control unit uses an averaging method to generate a virtual object on the computer display screen. The position of the virtual object is calculated based on the strength of the signal received. The movement of the virtual object on the computer display screen is in the same direction as and is proportional to the glove movement.

Abstract: An apparatus for preparing a plastic eyeglass lens includes a coating unit and a lens curing unit. The apparatus is preferably configured to allow the operation of both the coating unit and the lens curing unit. The apparatus may also include a post-cure unit and a controller. The controller is configured to control the operation of the coating unit, the lens curing unit and the post-cure unit. The lens forming unit may include an LCD filter disposed between activating light sources and a mold assembly. The mold assembly preferably includes two mold members held together by a gasket. The gasket preferably includes four protrusions spaced at 90 degree intervals about the gasket. A lens forming composition may include a first photochromic compound, a second photochromic compound and a light effector. The light effector may alter the color of a lens when exposed to photochromic activating light, when compared to a lens formed from a lens forming composition which does not include a light effector.

Abstract: A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is “soft” and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

Abstract: A surface processor uses an environmental profile to determine the sub-surface length of tubing disposed in a well bore. Information relating to tubing properties is stored in a memory module of the surface processor. The environmental profile includes data relating to well bore ambient conditions and the operating parameters of well equipment. Surface processor calculates the tubing elongation or length reduction corresponding to the environmental profile. Surface processor may repeat this process to develop a measured depth chart for a well. Logging operations performed in conjunction with the sub-surface length calculations allows formation data to be associated with the measured depth chart.

Abstract: A geographic-based communications service system has a mobile unit for transmitting/receiving information, and access points connected to a network. The access points are arranged in known geographic locations and transmit and receive information from the mobile unit. When one of the access points detects the presence of the mobile unit, it sends a signal to the network indicating the location of the mobile unit and the information requested by the mobile unit. Based on the signal received from the access point, the network communicates with information providers connected to the network and provides data to the mobile unit through the access point corresponding to the location of the mobile unit.

Abstract: A drop-in test structure fabricated upon a production integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology are described. The test structure may be fabricated upon an integrated circuit elevational profile formed according to a subset of steps within a sequence of steps of the integrated circuit production methodology that culminates in a production integrated circuit intended for use by a consumer. According to an embodiment, the integrated circuit elevational profile may be fabricated according to a majority of the sequence of steps. Alternatively, the integrated circuit elevational profile may be fabricated according to a minority of the sequence of steps. The test structure may be fabricated upon die sites designated to receive the test structure. Alternatively, the test structure may be fabricated upon die sites otherwise intended for operable integrated circuits.

Abstract: A computer system includes a chassis, electronic circuitry, a plurality of removable power supply units, and a power distribution mechanism to which the power supply units are connectable. The chassis includes at least one connector for effecting a connection to a first, chassis, ground potential. The electrical circuitry is connected to a second, logic, ground potential. Each of the power supply units is provided with a separate removable grounding plate for selectively coupling chassis ground to logic ground. The use of a power distribution mechanism with a plurality of removable power supply units enables redundancy for the power supply units, whereby the system can remain powered when one of the power supply units fail. The use of the grounding plates for each of the power supply units enables reliable connection of the electrical and chassis grounds can be effected, even when one of the power supply units and/or its connecting cable is faulty.

Abstract: A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a pair of global error correction codes, referred to generally as an untwisted global error correction code and a twisted global error correction code. Data at corresponding bit positions within the logical groups are conveyed through a common component. The untwisted global error correction code may be equivalent to the result of generating an individual error correction code for each logical group and XORing the collection of individual error correction codes together.

Abstract: A signal analysis system and method for analyzing an input signal acquired from a mechanical system. The mechanical system may include at least one rotating apparatus. The signal analysis system may include an input for receiving samples of an input signal acquired from the mechanical system, wherein the input signal is sampled in time, and wherein the input signal comprises a plurality of order components. The signal analysis system may also include a processor coupled to the input and a memory medium coupled to the processor which stores analysis software.