Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgement for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A data signal attenuator is constructed to include an optocoupler, a biasing source for powering the optocoupler and restoring the amplitude of an originally transmitted signal, and a connector for connecting the attenuator to the exterior of a receiving device. When connected to the receiver, the attenuator electrically connects a single-ended data transmission line to the receiving device. The external connection of the attenuator to the receiving device thus enables existing receivers to have the benefits of an optocoupler based attenuator without the necessity of redesign.

Abstract: An apparatus for identifying memory requests originating on remote I/O devices as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor, cache coherence directory and cache coherence controller all coupled to a host bridge unit (North bridge). The I/O device transmits requests for data to an I/O bridge unit. The I/O bridge unit forwards the request for data to the host bridge unit and asserts a sideband signal to the host bridge unit if the request is for non-cacheable data. The sideband signal informs the host bridge unit that the memory request is for non-cacheable data and that the cache coherence controller does not need to perform a cache coherence directory lookup. For cacheable data, the cache coherence controller performs a cache coherence directory lookup to maintain the coherence of data stored in a plurality of processor caches in the computer system.

Abstract: An apparatus and method for generating virtual addresses for different types of memory models using an existing address generation unit. A processor can be configured to operate using either a segmented memory model or a flat memory model according to an operating mode. When the processor is operating using a segmented memory model, it can use the base address of a segment register to calculate a virtual address. When the processor is operating using a flat memory model, it can use the base address of a pseudo segment register to calculate a virtual address. In this manner, the processor can use existing address generation techniques to generate a virtual address for either a segmented memory model or a flat memory model.

Abstract: A computer system having a highly parallel system architecture with multiple central processing units, multiple core logic chipsets and pooled system memory is provided with one or more AGP ports capable of connection to AGP devices. A memory manager is provided within the operating system for allocating pooled memory resources without regard to the location of that memory. A method is presented for dynamically allocating memory for the AGP device that is located on the same core logic chipset to which the AGP device is connected. By allocating local memory instead of allocating memory on remote core logic units, the AGP device can access the needed memory quickly without memory transmissions along the host bus, thereby increasing overall performance of the computer system.

Abstract: A phase-locked loop circuit and method for providing for compensation for an offset. A phase-locked loop circuit comprises a phase detector, a compensation circuit, a loop filter, and a VCO. The phase detector is coupled to receive a first input signal and a second input signal. The phase detector is configured to output one or more of a plurality of output signals indicative of a difference between the first input signal and the second input signal. The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals. The compensation circuit is further configured to provide a plurality of compensated output signals. The loop filter is coupled to receive the compensated control signals. The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal.

Abstract: Mixed metal carbide catalysts that are active for catalyzing the net partial oxidation of methane to CO and H2 are disclosed, along with their method of making. The preferred catalysts of the invention comprise a mixture of at least two carbided metals that are prepared by the reaction of the metal oxides, alkoxides or nitrates with a hydrocarbon of the formula CnH2n+2 wherein n is an integer from 1 to 4. Optionally, the catalysts include an additional promoter and/or a catalyst support. Preferred catalysts are at least 50 wt % molybdenum, tungsten or chromium, and also contain a second metal selected from the group consisting of molybdenum, tungsten, vanadium, chromium, iron, niobium, tantalum, rhenium, cobalt, copper, tin and bismuth.

Abstract: A hot dockable computer system comprises an enhanced expansion bus bridge for coupling the computer system to a docking station. The enhanced bus bridge includes an ACPI control unit for controlling the power state of the bridge device and associated buses. The ACPI control unit receives a docking signal from a docking connector on the computer that is asserted to indicate when a docking sequence has completed. When the docking signal is asserted, the bus bridge transmits a PME interrupt to the operating system, which activates the bus bridge. The bus bridge further includes a plurality of switches coupling the expansion bus signals in the computer system to the expansion bus signals in the dock. The ACPI control unit opens the switches when the bus bridge is deactivated, decoupling the expansion bus in the computer from the expansion bus in the dock. Similarly, the ACPI control unit deasserts the control signal to close the switches when the bus bridge is activated, connecting the expansion buses.

Abstract: A computer system, bus interface unit, and method is provided for programmably modifying securable resources of the computer. Those resources may be devices which can be coupled to peripheral buses of the computer, or which may contain or allow access to sensitive information that must be secured against improper access. The security system thereby functions to block accesses to certain devices based on the status of the user seeking access. Passwords stored in the security system are matched against locally and distally entered passwords from either the user of that particular computer system, an administrator of a subset of localized computer systems, or a system administrator in charge of all networked computer systems. The present security system is thereby hierarchical in nature and can be programmed by the system administrator such that the assignment of unlocked signals arising from password comparisons can be programmably mapped to various securable devices.

Abstract: A removable, compact and easily accessible cylinder impurity remover apparatus has a wiping position for removing impurities from a rotatable printing plate cylinder on a printing press and a non-wiping position. The impurity remover removeably slides or swings into position for wiping a plate on the plate cylinder. Most preferably, a pressure source acts on two pistons to move two parallel reciprocably mounted shafts and a wiper blade mounted thereon to the wiping position. Both the pistons and shafts are preferably contained inside an actuator bar, which is mounted parallel to a printing plate cylinder. As the wiper blade moves forward to the wiping position, a bias member is compressed and remains compressed until the pressure source stops, allowing the bias member to automatically retract the reciprocably mounted shafts and wiper blade to a non-wiping position.

Abstract: A relay multiplexing system which provides improved safety from hazardous voltage conditions. The relay multiplexing system comprises a relay multiplexer module and a terminal block which connects to the relay multiplexer module. The relay multiplexer module and corresponding terminal block incorporate a design according to the present invention whereby power can only be provided to the respective relays when the corresponding terminal block is connected to the respective relay multiplexer module. The terminal block is required to form an electrical path between the power supply in the relay multiplexer module and the relays. Thus, when the terminal block is removed from the corresponding relay multiplexer module, power is unable to be provided to the relays, thereby ensuring safety from hazardous voltages which could otherwise appear on exposed pins of the connector.

Abstract: A microprocessor configured to predecode variable length instructions in a massively parallel fashion is disclosed. The microprocessor may comprise a prefetch fetch unit configured to read instruction bytes from memory and a plurality of predecode unit configured to receive and predecode the instruction bytes. The predecode units are configured to operate separately and in parallel to generate one or more predecode bits per instruction byte. The microprocessor may further include a predecode bit correction unit configured to receive, verify, and correct the predecode bits from the parallel predecode units. A computer system and method for predecoding instructions are also disclosed.

Abstract: A microprocessor configured to rapidly decode variable-length instructions is disclosed. The microprocessor is configured with a predecoder and an instruction cache. The predecoder is configured to expand variable-length instructions to create fixed-length instructions by padding instruction fields within each variable-length instruction with constants until each field reaches a predetermined maximum width. The fixed-width instructions are then stored within the instruction cache and output for execution when a corresponding requested address is received. The instruction cache may store both variable- and fixed-width instructions, or just fixed-width instructions. An array of pointers may be used to access particular fixed-length instructions. The fixed-length instructions may be configured to all have the same fields and the same lengths, or they may be divided into groups, wherein instructions within each group have the same fields and the same lengths.

Abstract: Nonlinear control algorithms to compensate for kinematic error in harmonic drives provide a solid basis to improve their performance of harmonic drives in precision positioning applications. The present closed loop control algorithms compensate for kinematic error irrespective of its form in both set-point and trajectory tracking applications.

Abstract: A graphics system and method for reducing redundant transformation and lighting calculations performed on vertices that are shared by more than one geometric primitive is disclosed. The amount of data transmitted in certain data blocks may be reduced by incorporating a multicast/unicast bit into each data block. This bit may then be set to instruct the control unit to use the current 3D geometry data or state information for subsequent vertices. This may increase efficiency by allowing subsequent vertices using the same 3D geometry data to transfer less data. Conversely, if a vertex has wholly independent 3D geometry data, then its multicast/unicast bit may be set to invoke use of the current 3D geometry data on the current vertex as opposed to all future vertices. The reduction in redundant calculations is accomplished by delaying the formation of geometric primitives until after transformation and lighting has been performed on the vertices.

Abstract: A system and method for recording and addressing out of control (OOC) events in a semiconductor processing line. The method includes steps of (a) opening OOC entries in an OOC database, and (b) working the OOC entries. Opening an OOC entry is performed in response to one or more OOC events in wafer lots being processed in the semiconductor processing line. A lot record addresses an isolated occurrence pertaining to one wafer lot. An issue record addresses a trend of repeated defects or failures. Opening an OOC entry in the OOC database preferably includes assigning and recording an “owner” responsible for addressing the OOC entry. Working the OOC entries includes opening activity records for the OOC entries, receiving user input on corrective measures, and recording the measures in the activity records. The method preferably also includes steps of (c) closing OOC entries after working the OOC entries, and (d) reassigning OOC entries if ownership is transferred for the entries.

Abstract: A microprocessor having an instruction queue capable of out-of-order instruction dispatch and efficiently detect full conditions is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. Instead of determining exactly how many empty storage locations are present in the queue, the control logic may be configured to determine whether the number of non-overlapping strings of empty storage locations is greater than or equal to the number of estimated instructions currently on their way to being stored in the instruction queue.

Abstract: A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.

Abstract: A break event in a computer system that can operate in one of a plurality of modes, such as a high performance mode and a low power mode is initiated only be logic that that detects when the transition between modes is complete. In the high performance mode, the CPU clock is faster than in the low power mode. The CPU voltage may also be higher in the high performance mode than in the low speed mode. The low power mode may be desirable for a portable computer operating from battery power in order to conserve the battery's charge. The computer system preferably transitions its CPU to a “sleep” state during the mode switch and precludes devices not associated with the mode transition from “waking” the CPU and disturbing the completion of the mode switch. Accordingly, only logic that detects the end of the mode switch can break the CPU out of its sleep state.

Abstract: A portable notebook computer having a thickness of only one inch is obtained by provision of a computer housing containing a keyboard assembly and a motherboard positioned directly below the keyboard assembly, the keyboard assembly and the motherboard thereby defining a region in the enclosure. The other components comprising the computer; i.e. a hard disk drive, a PCMCIA option slot, a trackball assembly, and a DC to DC convertor, are positioned in an adjacent and generally co-planar relationship with this region. A battery housing is mounted externally on the computer housing for supplying electrical power to the computer.