Abstract: A Fischer-Tropsch catalyst comprising a catalytically active first metal selected from the group consisting of at least one metal selected from the group consisting of iron, nickel, cobalt, chromium, and mixtures thereof, at least one second metal selected from the group consisting of silver, iron, zinc, copper, platinum, zirconium and combinations thereof; and a matrix structure comprising a polymer selected from the group consisting of polyacrylates and polymethacrylates. The first and second metals are incorporated into the polymer.

Abstract: An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. A first via may extend perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via may extend perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors may cause the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit.

Abstract: A circuit and method are disclosed herein for a crystal oscillator, wherein the Q of the resonant network is not reduced through the loading effects of the oscillator's resistive bias network. The oscillator is configured as an operational transconductance amplifier (OTA) coupled to the resonant network. The OTA creates a negative resistance, which compensates for energy lost to resistance within the resonant network, thereby sustaining oscillation at the resonant frequency. Instead of using bias resistors to set and maintain the operating point of the oscillator, another OTA (with a high output impedance) injects a current into the resonant network to bias the oscillator. Advantageously, this technique avoids the reduction in Q that occurs when bias resistors are connected across the high effective parallel resistance of the resonant crystal. The higher Q benefits frequency stability and phase jitter characteristics of the oscillator.

Abstract: A system and method for compression of surface normals in three-dimensional graphics data. The method comprises compressing a normal by identifying the location of a first point located at the intersection of the surface of a predetermined sphere (centered on the origin of a set of x-y-z axes) and a vector extended from the origin in a direction specified by the coordinate values of the normal. Identification of the first point includes specifying an index value and one or mapping values. The index value is usable during decompression to identify a second point on the sphere from a plurality of points in a predetermined surface region (such as a predetermined sextant of a predetermined octant region). In one embodiment, the index includes a &thgr; component and a &phgr; component which are usable to locate the second point.

Abstract: In a system and method for displaying status of critical indicators or variables, icons representing the indicators are displayed in superposition with a reference shape. The reference shape is divided into “higher-interest” and “lower-interest” portions, such that display of an icon over the higher-interest portion of the reference shape indicates a higher-interest value of the corresponding variable. The reference shape is preferably elongated horizontally, with its upper portion designated as the higher-interest portion and its lower portion designated the lower-interest portion. Each monitored variable may be allocated a vertical “slice” of the reference shape, such that the position of the corresponding icon when the variable is in the higher-interest state is laterally aligned with the position of the icon when the variable is in the lower-interest state.

Abstract: A system and method are presented for a write buffer that combines capabilities and features implemented in separate, specialized buffers in prior art microprocessors. The write buffer receives data records from a CPU and subsequently transfers them to a memory bus. In addition to the data records themselves, each location in the buffer contains a complement of control bits, which determine the mode in which the associated record will be transferred to the memory bus. The use of these bits allows the buffer to perform memory transfers associated with a write-back data cache or an EJTAG test module, as well as more conventional transfers traditionally performed by a write buffer. The combination of these multiple capabilities in a single write buffer is believed to simplify the design of the bus interface unit in a microprocessor incorporating the principles disclosed herein.

Abstract: An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.

Abstract: A charged particle imaging system may be used to perform package-level failure analysis by providing a Capacitive Coupling Voltage Contrast image of a portion of the semiconductor package. Preliminary failure analysis using Time Domain Reflectometry may determine whether a defect lies either outside or within the semiconductor package substrate. The semiconductor package may be prepared such that sequential layers of the package may be removed until electrical testing determines the location of a defect on a layer of the package. An alternating signal may be supplied to an exposed trace conductor on the layer of the package substrate on which the defect is located. A portion of the trace conductor may be imaged with a charged particle imaging system to produce a voltage-induced contrast image of the trace conductors.

Abstract: A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder circuit generates a first input command which is then passed, in sequence, by the first and second multiplexers. Conversely, if the data transfer request relates to a read or write burst which will burst over a page of the memory, the second input command decoder circuit generates second and third input commands. The second input command passes through the second multiplexer circuit while the third input command is held in a command register. The third input command is subsequently passed through the first and second multiplexers.

Abstract: A method, system and catalysts for improving the yield of syngas from the catalytic partial oxidation of methane or other light hydrocarbons is disclosed. The increase in yield and selectivity for CO and H2 products results at least in part from the substitution of H2S partial oxidation to elemental sulfur and water for the combustion of light hydrocarbon to CO2 and water.

Abstract: An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe pads. The other row of probe pads is placed toward the interior of the integrated circuit. The rows of bonding pads and probe pads extend along parallel axis around all four sides of the integrated circuit. Every other bonding pad within one row of bonding pads is connected to every other probe pad within the scribe area, and every other bonding pad within the other rows of bonding pads is connected to every probe pad within the row of probe pads interior to the integrated circuit. This allows a fan-out configuration of the bonding pads to probe pads for purposes of probing electrical performance of the integrated circuit without having to use selected ones of the bonding pads.

Abstract: An integrated circuit device is disclosed having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary scan chain, a register, and a test access port. The application logic is the logic that provides the intended function of the chip. The BIST unit is configured to apply test patterns to the application logic to verify its functionality. The boundary scan chain is configured to sample input signals to the application logic and to control output signals from the application logic. The register stores an operational mode parameter for the BIST. The test access port provides external access to the boundary scan chain and the register, and is configured to control a clock signal to the BIST unit in accordance with the BIST operational mode parameter.

Abstract: A video system is disclosed that processes OSD images and displays the OSD images on a display. At least some of the OSD images are represented by data sets that do not include a color palette. Each OSD data set includes a header comprising multiple bits of status and control information. One of the control bits indicates whether the OSD data set includes a color palette. Preferably that control bit is set to indicate no color palette in present and cleared to indicate the inclusion of a color palette in the OSD data set. By not including a color palette in an OSD data set, the corresponding OSD image can be represented with a smaller data set and can be transferred across a bus with a smaller bandwidth. If the control bit is set, indicating the absence of a color palette in the OSD data set, a color palette included in another OSD data set is used instead to draw the desired OSD image.

Abstract: An acoustic logging tool including an elongated body, one or more acoustic transmitters, one or more acoustic receivers, and a broadband acoustic absorption region. A substantial portion of the broadband acoustic absorption region is between the transmitter and the receiver. The acoustic energy absorber includes a first absorber for absorbing a first mode of acoustic energy and a second absorber for absorbing a second mode of acoustic energy. The acoustic absorption material used to make the acoustic absorbers has an acoustic impedance between 20% and 120% of the material used to construct the acoustic logging tool. The acoustic logging tool includes an elongated hollow tool body, an insert configured to be inserted into the tool body, and a ring configured to be inserted onto the insert. A first element is supported by the ring and exposed to a pressure field, and a second element is supported by the ring and exposed to a pressure field.

Abstract: The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may include a semiconductor memory device, a cache memory device and a prefetch unit. The system may also include a memory bus to couple the semiconductor memory device to the prefetch unit. The system may further include a circuit coupled to the memory bus. The circuit may detect a branch instruction within the sequence of instructions, such that the branch instruction may target a loop construct. A circuit may also be contemplated herein. The circuit may include a detector coupled to detect a loop within a sequence of instructions. The circuit may also include one or more counting devices coupled to the detector. A first counting device may count a number of clock cycles associated with a set of instructions within a loop construct.

Abstract: A process is herein described for analyzing an integrated circuit chip for defects by observing changes in the appearance of a liquid crystal applied to the backside of the integrated circuit. The process includes spreading a thin film of a liquid crystal material on the backside of the integrated circuit. Using an optical microscope, the liquid crystal film is optically inspected as the chip is biased.

Abstract: Provided is a catalyst system for polymerization of monomer having at least one Ziegler-Natta polymerizable bond comprising: c) a supported Ziegler-Natta transition metal catalyst component comprising a Group 15 atom having two groups selected from the group consisting of alkyl and aryl, wherein the support is a magnesium halo dialkylamide; and d) an effective co-catalyst.

Abstract: A processor employs an instruction queue and a dependency vector generation unit. The dependency vector generation unit generates a dependency vector for each instruction operation. Particularly, a dependency vector corresponding to a first instruction operation may be indicative of an ordering dependency between the first instruction operation and a prior instruction operation even if the first instruction operation does not have an operand dependency on the prior instruction operation. The instruction queue inhibits dependencies until each dependency within the dependency vector is satisfied.

Abstract: A molybdenum-loaded crystalline aluminosilicate molecular sieve that exhibits the MFI crystal structure and has a silica-to-alumina ratio of about 50:1 is useful for aromatizing a hydrocarbon feed stream. The crystalline aluminosilicate preferably has an external surface acidity selectively passivated by means of an amorphous silica layer. A process for the aromatization of methane comprises a one- or multi-step process that contacts a feed stream comprising at least methane with a catalyst composition comprising the preferred molecular sieve, at hydrocarbon conversion conditions that include a temperature of 600-800° C., a pressure of less than 5 atmospheres absolute and a Weight Hourly Space Velocity (WHSV) of 0.1-10 h−1, with the external surface acidity of the crystalline aluminosilicate preferably selectively passivated by an amorphous silica layer. C6-plus aromatic hydrocarbons are preferably recovered from the process by means of an intermediate separation step.

Abstract: A multiport testing procedure capable of detecting faults that occur between static random access memory ports as well as traditional cells faults uncovers all possible faults and covers all cells in the memory, without placing architectural constraints on the memory. While executing a test sequence on one port of the memory array, concurrent memory accesses are performed through other ports in the memory. If a fault exists between the port under test and any other port, then the concurrent operations interfere with the values read and/or written on the port under test, and the test uncovers the fault. Thus, for any one test port, the interport test requires only as many memory operations as the associated single port test, keeping test time to a minimum. One embodiment detects faults between the test port, which is a read/write port, and any other port, including read ports and write ports, comprising six passes through the memory.