Patents Represented by Attorney, Agent or Law Firm Conley, Rose & Tayon
  • Patent number: 6513385
    Abstract: A method and apparatus for analyzing a deposited layer on the inner surface of a fluid container wall having inner and outer surfaces are disclosed. One embodiment of the method comprises (a) transmitting an acoustic signal from a transmitter at a first distance from the outer surface of the wall; (b) receiving a first received signal A, comprising a reflection from the wall outer surface; (c) receiving a second received signal B, comprising a reflection from the wall inner surface; (d) receiving a third received signal C from the wall inner surface; (e) calculating a coefficient Rwp from A, B and C, and (f) calculating a coefficient Rpd from A, B and Rwp, and calculating the acoustic impedance of the deposited layer Zd from Rwp, Rpd, and Zw, where Zw is the acoustic impedance of the material between the transmitter and the wall outer surface.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: February 4, 2003
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Wei Han, Vimal V. Shah, James R. Birchak, Bruce H. Storm, Jr., Rajnikant M. Amin, Bayram Kalpakci, Fouad Fleyfel
  • Patent number: 6515287
    Abstract: A magnetic lens configured to apply a magnetic field to a charged particle beam is provided. The magnetic lens may include an outer pole piece and an inner pole piece. The outer pole piece may have at least two sectors and at least two slots. The magnetic lens may also have a primary coil winding interposed between the outer pole piece and the inner pole piece. In addition, the magnetic lens may have a number of sector coil windings, and each sector of the outer pole piece may be coupled to one sector coil winding. A magnetic potential of the outer pole piece relative to the inner pole piece may be generated by applying a current to the primary coil winding. A separate magnetic potential of each sector may also be generated by applying a current to the respective sector coil windings of each sector of the outer pole piece.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: February 4, 2003
    Assignee: KLA-Tencor Technologies Corporation
    Inventor: John A. Notte, IV
  • Patent number: 6511514
    Abstract: A lightweight foot prosthesis is claimed, having a heel, a toe, and a raised instep, an ankle joint incorporated in the foot and capable of motion around each of three perpendicular axes. The foot includes a dorsal member and a plantar member. The prosthesis includes a device for limiting rotation of the ankle joint about at least one of the axes.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: January 28, 2003
    Inventor: Michael T. Wilson
  • Patent number: 6510909
    Abstract: A rolling cone bit includes at least one cone cutter having a gage row of cutter elements and a first inner row of near but off-gage cutter elements that are positioned so as to divide the sidewall and bottom hole cutting duty so as to enhance bit durability, maintain borehole diameter and improve ROP. The off-gage distance of the first inner row of cutter elements is defined for various bit sizes to optimize the division of cutting duty. The distance that the first inner row of cutter elements are off-gage may be constant for all the cones on the bit or may be varied among the various cones to balance the durability and wear characteristics on all the cones of the bit.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: January 28, 2003
    Assignee: Smith International, Inc.
    Inventors: Gary Ray Portwood, Gary Edward Garcia, James Carl Minikus, Per Ivar Nese, Dennis Cisneros, Chris Edward Cawthorne
  • Patent number: 6509270
    Abstract: A method is provided for processing a semiconductor topography. In particular a method is provided in which a greater pressure may be applied to a first portion of a semiconductor topography than in a second portion of the topography. As such, a method is provided in which a portion of an upper layer in a region adjacent to an outer edge of the semiconductor topography is polished at a faster rate than a portion of the upper layer in a region comprising the center of the topography. Consequently, the method may subsequently provide a manner in which a substantially planar upper surface may be formed across a semiconductor topography including a region adjacent to an outer edge of the semiconductor topography. Alternatively, regions of an upper layer of a semiconductor topography polished at a faster rate than other regions may occur at various locations across the topography.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: January 21, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventor: Ruediger Held
  • Patent number: 6510508
    Abstract: A translation lookaside buffer (TLB) flush filter. In one embodiment, a central processing unit includes a TLB for storing recent address translations. A TLB flush filter monitors blocks of memory from which address translations have been loaded and cached in the TLB. The TLB flush filter is configured to detect if any of the underlying address translations in memory have changed. If no changes have occurred, the TLB flush filter may then prevent a flush of the TLB following the next context switch. If changes have occurred to the underlying address translations, the TLB flush filter may then allow a flush of the TLB following a context switch.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: January 21, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gerald D. Zuraski, Jr., Michael T. Clark
  • Patent number: 6510522
    Abstract: A computer system, bus interface unit, and method are provided for securing certain devices connected to an I2C bus. Those devices include any device which contains sensitive information or passwords. For example, a device controlled by a I2C-connected device bay controller may contain sensitive files, data, and information to which improper access may be denied by securing the device bay controller. Moreover, improper accesses to passwords contained in non-volatile memory connected to the I2C bus must also be prevented. A bus interface unit coupled within the computer contains registers, and logic which compares the incoming I2C target and word addresses with coded bits within fields of those registers. If the target or word address is to a protected address or range of addresses, then an unlock signal must be issued before the security control logic will allow the target or word address to access the I2C bus or addressed device thereon.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: January 21, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: David F. Heinrich, Hung Q. Le, Paul B. Rawlins, Charles J. Stancil
  • Patent number: 6507044
    Abstract: A method for position-selective and material-selective etching of silicon, and examination structures formed using the method, are presented. A semiconductor topography is exposed to an electron beam in the presence of xenon difluoride (XeF2) gas. The beam is scanned over a portion of the semiconductor topography, and silicon portions of the topography contacted by the electron beam and the XeF2 gas are etched. Non-silicon portions, such as dielectrics, metals, and/or metal silicides, are not believed to be etched. Shorter exposure times may be used to remove polycrystalline silicon portions of a topography, while leaving monocrystalline silicon portions intact. Removal of silicon and non-silicon portions of the topography by other means may be used to expose silicon portions of the topography. The electron beam controlled etching recited herein may be used alone or combined with such removal by other means to form examination structures for use in evaluation of semiconductor manufacturing techniques.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: January 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Miguel Santana, Jr., Markangelo S. D'Souza
  • Patent number: 6507166
    Abstract: The control device carries out a control of the induction machine based upon a flux estimation performed by means of a Luenberger state observer, the estimation error of which can be defined by means of a matrix having a plurality of eigenvalues, the magnitude of each of which is proportional to the magnitude of a respective pole of the induction machine, and the phase of each of which is rotated with respect to the phase of the corresponding pole of the induction machine by a given angle of rotation.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: January 14, 2003
    Assignee: C.R.F. Societa Consortile per Azioni
    Inventors: Roberto Maceratini, Giovanni Barba
  • Patent number: 6507343
    Abstract: A method of configuring information for display includes assigning continuum labels to pieces of information, or information units, accessible by a computer system. The continuum labels may be used in arranging the information units into ordered sequences, or continuum arrangements. Criteria for ordering of the information units within the continuum arrangement may include, for example, the level of detail of the subject matter of the information units or the degree to which the subject matter of an information unit is related to that of a reference information unit. Formation of continuum arrangements may be done by entering data into a data structure or rules database, or by a method of using a graphical user interface to establish sequences of icons representing information units. Forming continuum arrangements to configure information may allow display of the information in a form allowing rapid, convenient viewer access to desired pieces of information.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corp.
    Inventor: Margaret Gardner MacPhail
  • Patent number: 6507672
    Abstract: An improved multimedia encoder having features advantageous for use in a computer system. These features provide for the reduction of bandwidth and storage requirements, the enhancement of noise immunity, the evening of computational loading, and the use of multimedia drives for general purpose data storage. In one embodiment, the encoder receives image data representing a sequence of video frames and display text data representing a sequence of text fields to be overlaid on the sequence of video frames. The multimedia encoder produces a compressed video frame only for each subsequent video frame which is different from the current video frame. After each video frame is compressed, it becomes the current frame. The multimedia encoder provides error correction encoding to enhance noise immunity, and performs interframe compression using a dynamic search area to even out computational loading.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: January 14, 2003
    Assignee: LSI Logic Corporation
    Inventors: Daniel Watkins, Gregg Dierke
  • Patent number: 6502634
    Abstract: The present invention relates generally to the treating of wells, and more particularly to a method and device that are capable of detecting the position of a fluid interface so that a well treatment can be placed with greater along hole depth precision in a given hydrocarbon producing well than previously. More particularly, an embodiment of the invention includes a method for accurately placing a well treatment fluid in a well, comprising: pumping a first fluid into a first part of the well until an interface is formed between the first fluid and a second fluid; extracting information regarding at least one fluid property of the first and second fluids with first and second to sensors positioned in the first and second fluids respectively; and exchanging information between the first and second sensors and a telemetry unit.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: January 7, 2003
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Michael Evans, Andrew Penno
  • Patent number: 6505313
    Abstract: A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: January 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Tuan Phan, William Schwarz
  • Patent number: 6505258
    Abstract: A system is disclosed for allowing surprise insertion and removal of a peripheral device from the bays of a portable computer system. The peripheral device may be inserted or removed when the portable computer system is powered off, powered on, or in standby or sleep mode. The peripheral device may be any one of a multitude of devices corresponding to the IDE, ATAPI or FLOPPY standard. Insertion or removal of the device is operating system and BIOS independent. A constantly executing detection process determines when a peripheral device has been inserted into or removed from a bay. A multilevel device driver allows layered functionality and simplified interfacing between the operating system and computer system and peripheral hardware. Layering of the multilevel device driver allows simplified BIOS firmware. Identification and configuration of the peripheral device is handled by a IDE/ATAPI bridge device driver that is capable of recognizing any IDE, ATAPI or FLOPPY device inserted into a bay.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: January 7, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Premanand Sakarda, Lan Wang
  • Patent number: 6505260
    Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: January 7, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Kenneth T. Chin, C. Kevin Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens
  • Patent number: 6505308
    Abstract: A fast method and apparatus for built-in self-repair (BISR) of memory arrays is disclosed. In one embodiment, an integrated circuit includes a repair circuit coupled between the address decoder and the memory array. The address decoder receives memory addresses and asserts corresponding word lines. The memory array has default words associated with the word lines, but also includes extra words. By default, the repair circuit maps the word lines from the address decoder to the memory array word lines for the default words. However, the repair circuit includes at least one latch for each of the decoder word lines. When a latch is set, the repair circuit isolates the decoder word line from the default word and remaps the decoder word line to an extra word in the memory. The latches remain set while as long as power is applied, so that accesses to faulty memory words are automatically rerouted without any additional overhead relative to accesses to functional memory words.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: January 7, 2003
    Assignee: LSI Logic Corporation
    Inventor: William Schwarz
  • Patent number: 6502639
    Abstract: Accordingly, an improved pumping system is herein disclosed. In one embodiment, the pumping system includes a subsurface pump, a tubing string, and a surface pumping unit. The subsurface pump is anchored downhole and driven by repeated upward and downward motion of the tubing string. The subsurface pump pumps fluids to the surface via the tubing string. The upward and downward motion of the tubing string is imparted by any suitable surface pumping unit such as, e.g. a beam pumping unit or a hydraulic pumping unit. This pumping system advantageously provides for a minimal number of strings downhole, requiring at most only (1) casing and (2) the production tubing. Accordingly, the well may be drilled using a very slender hole, thereby allowing for sharply reduced drilling and production costs.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: January 7, 2003
    Inventor: Humberto F. Leniek, Sr.
  • Patent number: 6501469
    Abstract: A method of configuring information for display includes assigning continuum labels to pieces of information, or information units, accessible by a computer system. The continuum labels may be used in arranging the information units into ordered sequences, or continuum arrangements. Criteria for ordering of the information units within the continuum arrangement may include, for example, the level of detail of the subject matter of the information units or the degree to which the subject matter of an information unit is related to that of a reference information unit. Formation of continuum arrangements may be done by entering data into a data structure or rules database, or by a method of using a graphical user interface to establish sequences of icons representing information units. Forming continuum arrangements to configure information may allow display of the information in a form allowing rapid, convenient viewer access to desired pieces of information.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: December 31, 2002
    Assignee: International Business Machines Corp.
    Inventor: Margaret Gardner MacPhail
  • Patent number: 6502203
    Abstract: A method and system of quorum negotiation utilizing power mains. Unlike current systems, this communication is provided as a secondary channel, with the primary channel being a standard network system. By using this technique, if the heartbeat is lost over the primary communication system, the secondary, power-mains system can be used to check the heartbeat to validate whether or not the “lost” system is still in operation. If communication cannot be established over the power mains, it is assumed that the “lost” system is down and should be dropped from any cluster.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: December 31, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Dwight L. Barron, Michael F. Angelo
  • Patent number: D468542
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: January 14, 2003
    Inventors: Pieter Jacob Machiel Hennekes, Martinis Johannes Knibbe