Patents Represented by Attorney, Agent or Law Firm Conley, Rose & Tayon
  • Patent number: 6499538
    Abstract: Methods and apparatus are described for forming a window of optimum dimensions in casing wall. A window of maximum width is cut when the center line of the mill tool is located inside of the inner diameter of the casing where a maximum amount of casing is drilled away by the mill tool. A whipstock is described which deviates the mill tool outwardly so that the center line of the mill tool is in approximately this position. The whipstock then maintains the mill tool at this approximate location until a window of desired length is cut having a substantially maximum width.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: December 31, 2002
    Assignee: Smith International, Inc.
    Inventors: Charles H. Dewey, John E. Campbell
  • Patent number: 6499537
    Abstract: The well reference apparatus and method of the present invention includes a reference member preferably permanently installed within the borehole at a preferred depth and orientation in one trip into the well. The reference member provides a permanent reference for the location of all operations, particularly in a multi-lateral well. The assembly of the present invention includes disposing the reference member on the end of a pipe string. An orienting tool such as an MWD collar is disposed in the pipe string above the reference member. This assembly is lowered into the borehole on the pipe string. Once the preferred depth is attained, the MWD is activated to determine the orientation of the reference member. If the reference member is not oriented in the preferred direction, the pipe string is rotated to align the reference member in the preferred direction. This process is repeated for further corrective action and to verify the proper orientation of the reference member.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: December 31, 2002
    Assignee: Smith International, Inc.
    Inventors: Charles H. Dewey, John E. Campbell, Wei Xu
  • Patent number: 6498716
    Abstract: The present invention is a power distribution assembly for distributing power about a rack mounted server system. In particular, each chassis of a rack mounted server system is provided power through a power distribution assembly that is hinged to a back of the rack of the server system. Each of the power distribution assemblies may be in either an open position or a closed position. In a closed position, each of the power distribution assemblies is rotated to lie very close to a backplane board of a chassis of the server system. In an open position, each of the power distribution assemblies is swung around so that full access may be had to the backplane boards of the chassis in the server system.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: December 24, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Everett R. Salinas, Allen T. Morrison
  • Patent number: 6498460
    Abstract: A power management scheme for a computer system prioritizes battery charging. The scheme includes determining when the output of a power adapter, which powers a computer and a battery subsystem, has reached or is about to reach a threshold which may be the power budget for the computer system. When this happens, rather than throttling battery charging, the system throttles back an aspect of the computer. Alternatively, after the computer has been throttled back, if the power budget still is being exceeded or is about to be exceeded again, then battery charging can be throttled back. In yet another embodiment, battery charging can be throttled first, followed, if necessary, by computer throttling.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: December 24, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Lee W. Atkinson
  • Patent number: 6497286
    Abstract: An underwater well system in which an initially vertical drilling riser conduit (5A) is fixed by a template at the seabed in a non-vertical orientation. Drilling is carried out through wellhead in the template which also includes a valve tree allowing the production fluid to be brought to the surface along a line separate from the drilling riser conduit. The template may be a junction template allowing several wells to be drilled from a single template, or allowing the template to be connected by one or more drilling conduits to further templates such that a wide area of the seabed can be covered for a single drilling riser conduit.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: December 24, 2002
    Assignee: Cooper Cameron Corporation
    Inventor: Hans Paul Hopper
  • Patent number: 6499123
    Abstract: An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second plurality of signals in the debug mode. In one embodiment, the integrated circuit embodies a microprocessor. The microprocessor may include logic circuitry for enabling the second plurality of signals to be output from a multiplexer to the output pins in response to a predetermined event, such as a hit in an associated memory unit.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: December 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R. Greenley, Robert A. Cargnoni
  • Patent number: 6496950
    Abstract: A CAM testing procedure detects storage logic faults, comparison logic faults, and faults caused by interactions between the storage and comparison logic for both single port and dual port CAM's. To uncover faults in the storage logic, a series of read and write operations are performed, either using a standard test sequence, such as the March C algorithm, or any other desired test sequence. The CAM test, however, intermixes comparison operations with the read and write operations to uncover faults in the comparison logic. For dual port memories, the test sequence comprises executing comparison operations concurrently with the read and/or write operations, thus revealing faults between the storage and comparison logic. For single port memories, the test sequence comprises performing a comparison operation following the read/write operations at each address, immediately verifying the comparison logic at each address.
    Type: Grant
    Filed: August 11, 1999
    Date of Patent: December 17, 2002
    Assignee: LSI Logic Corporation
    Inventors: Jun Zhao, Mukesh Puri, V. Swamy Irrinki
  • Patent number: 6494272
    Abstract: The drilling assembly includes an eccentric adjustable diameter blade stabilizer having a housing with a fixed stabilizer blade and a pair of adjustable stabilizer blades. The adjustable stabilizer blades are housed within openings in the stabilizer housing and have inclined surfaces which engage ramps on the housing for camming the blades radially upon their movement axially. The adjustable blades are operatively connected to an extender piston on one end for extending the blades and a return spring at the other end for contracting the blades. The eccentric stabilizer also includes one or more flow tubes through which drilling fluids pass that apply a differential pressure across the stabilizer housing to actuate the extender pistons to move the adjustable stabilizer blades axially upstream to their extended position. The eccentric stabilizer is mounted on a bi-center bit which has an eccentric reamer section and a pilot bit.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: December 17, 2002
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Jay M. Eppink, David E. Rios-Aleman, Albert C. Odell
  • Patent number: 6496945
    Abstract: A computer system implementing a fault detection and isolation technique that tracks failed physical devices by identification (ID) codes embedded in each component of the computer for which the ability to detect faults and isolate failed devices is disclosed. The computer system comprises one or more CPU's, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU's, memory modules, and master control device. The master control device also connects to the CPU's and memory modules over a serial bus, such as an I2C bus. Each CPU and memory module includes an ID code that uniquely identifies and distinguishes that device from all other devices in the computer system. The computer also includes a non-volatile memory device coupled to the CPU for storing a failed device log which includes a list of ID codes corresponding to failed physical devices.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: December 17, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Darren J. Cepulis, Sid Young, Jr.
  • Patent number: 6494702
    Abstract: Apparatus for making a plastic lens. Apparatus includes a mold cavity and a cooling fluid distributor. The apparatus is adapted to produce a plastic lens from a liquid composition.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: December 17, 2002
    Assignee: Q2100, Inc.
    Inventors: Omar M. Buazza, N. Thornton Lipscomb, Stephen C. Luetke, John J. Robinson
  • Patent number: 6496904
    Abstract: The present invention provides for a method and an apparatus for encoding coherency tag information for a plurality of busses. A first processor bus is coupled to a host controller. A second processor bus is coupled to a host controller. The host controller is coupled to a single coherency tag bank. Coherency tag data from the first processor bus and the second processor bus is stored into the coherency tag bank. A location of a data set sought by the first processor and the second processor is determined using the coherency tag data.
    Type: Grant
    Filed: May 5, 1999
    Date of Patent: December 17, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Robert L. Noonan
  • Patent number: 6494100
    Abstract: An improved door closure indicator is provided. The indicator operates on pressure levels read within a pressurized chamber rather than from proximity switches coupled between the chamber and the door. If the door seals to the chamber, pressure within the chamber will quickly change, and the change will be read on a pressure sensor indicative of the door closure. According to one example, the chamber can comprise a vacuum chamber and the pressure sensor can be a vacuum monitor. Once vacuum is detected, it is determined with more absolutism that the door is actually closed rather than having to rely upon switch operation and/or alignment of the door activation mechanism to proximity switches arranged on the chamber housing.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: December 17, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventor: Norman L. French, Jr.
  • Patent number: 6492710
    Abstract: A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: December 10, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventor: Jeffrey T. Watt
  • Patent number: 6493079
    Abstract: A system and method for analyzing an object using a reduced number of cameras and/or a reduced number of acquired images. The system and method may be utilized in a machine vision application, e.g., in order to inspect manufactured objects. The method may operate to acquire an image, or a plurality of images, of the object. In order to reduce the number of images that need to be acquired, at least one of the acquired images includes visual information for two or more sides of the object. Such an image may be acquired by a camera positioned in any of various ways such that the camera can capture visual information for multiple sides of the object. The acquired images of the object may then be received by computer systems connected to the cameras and analyzed using image processing software.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: December 10, 2002
    Assignee: National Instruments Corporation
    Inventor: Ignazio Piacentini
  • Patent number: 6493836
    Abstract: A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: December 10, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Sompong P. Olarig, John E. Jenne
  • Patent number: 6493824
    Abstract: A secure system and method is provided for remotely waking a computer from a power down state. In one embodiment, a network interface card receives incoming data packets via a network connector. A control module is coupled to the network connector and is configured to search the incoming packets for a wake-up pattern. The control module also verifies that the packet's destination address matches the destination address of the network interface card. If the destination addresses match and a wake-up pattern is found, the control module decrypts an encrypted value from the incoming packet and compares the result to an expected value. A successful comparison causes the control module to assert a signal to wake up the host computer. Preferably, a standard public/private key pair encryption scheme is used, and the source of the data packet encrypts the expected value with a private key.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: December 10, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Manuel Novoa, Adrian Crisan
  • Patent number: 6493506
    Abstract: An optical disk system is presented which stores disk- and user-specific settings, along with an associated method. The optical disk system includes a disk drive unit for retrieving identification data and encoded video data stored upon an optical disk, an input device for inputting user settings, and a microprocessor memory unit having a non-volatile portion for storing the identification data and the user settings. Information specific to optical disks (e.g., DVDs) and users is stored within the non-volatile portion of the microprocessor memory unit. The user settings may include, for example, spoken language, video display format, audio volume setting, and subtitle language. The user settings may be retrieved and invoked, conveniently allowing a user to view a presentation (e.g., a movie), or to continue viewing an interrupted presentation, without having to reselect viewing and listening preferences. The identification data may include a portion of a title of the optical disk.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: December 10, 2002
    Assignee: LSI Logic Corporation
    Inventors: Brian F. Schoner, Darren D. Neuman, Brett J. Grandbois, Christopher Cubiss
  • Patent number: 6493802
    Abstract: According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: December 10, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Rahul Razdan, James B. Keller, Richard E. Kessler
  • Patent number: 6489371
    Abstract: A process is disclosed for producing hydrocarbons. The process involves contacting a feed stream comprising hydrogen and carbon monoxide with a catalyst in a reaction zone maintained at conversion-promoting conditions effective to produce an effluent stream comprising hydrocarbons. In accordance with this invention, the catalyst used in the process preferably includes at least cobalt, rhenium, and a promoter selected from the group including boron, phosphorus, potassium, manganese, and vanadium. The catalyst may also comprise a support material selected from the group including silica, titania, titania/alumina, zirconia, alumina, aluminum fluoride, and fluorided aluminas.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: December 3, 2002
    Assignee: Conoco Inc.
    Inventors: Wenchun Chao, Kamel M. Makar, Leo E. Manzer, Munirpallam A. Subramanian
  • Patent number: 6489378
    Abstract: High impact polystyrene having a predominant core-shell morphology is made by polymerizing styrene in the presence of polybutadiene using toluene as a solvent. The thermoplastic polymer composition is characterized by a continuous phase of polystyrene containing dispersed graft copolymer particles having a core-shell structure with a polystyrene core occluded inside a polybutadiene shell. The styrene is desirably batch polymerized using styrene/toluene mixtures of about 70:30 by weight in the presence of from about 9 to about 15 weight percent polybutadiene while flashing off the toluene solvent.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: December 3, 2002
    Assignee: Fina Technology, Inc.
    Inventors: Jose M. Sosa, Lu Ann Kelly