Patents Represented by Attorney, Agent or Law Firm Conley, Rose & Tayon
  • Patent number: 6550032
    Abstract: A multiport testing procedure capable of detecting faults that occur between static random access memory ports as well as traditional cells faults uncovers all possible faults and covers all cells in the memory, without placing architectural constraints on the memory. While executing a test sequence on one port of the memory array, concurrent memory accesses are performed through other ports in the memory. If a fault exists between the port under test and any other port, then the concurrent operations interfere with the values read and/or written on the port under test, and the test uncovers the fault. Thus, for any one test port, the interport test requires only as many memory operations as the associated single port test, keeping test time to a minimum. One embodiment detects faults between the test port, which is a read/write port, and any other port, including read ports and write ports, comprising six passes through the memory.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: April 15, 2003
    Assignee: LSI Logic Corporation
    Inventors: Jun Zhao, Mukesh Puri, V. Swamy Irrinki
  • Patent number: 6544483
    Abstract: An adsorbent gas scrubber is provided in which the processing efficiency of the gas generated during semiconductor manufacturing can be increased, as the idle time of the system is reduced. The above mentioned object and other objects are accomplished by an adsorbent gas scrubber in accordance with aspects of the present invention which comprise an induction tube being connected to a gas inlet attached with a first pressure gauge for measuring a pressure of the entered gas, and an adsorbent case placed adjacent to the induction tube. The adsorbent case contains a layered arrangement of multiple catalytic-adsorbent members which adsorb the gas that flows from the induction tube to a gas outlet attached with a second pressure gauge for measuring pressure of the processed gas being discharged. A series of gas passage tubes placed at the bottom portion of the induction tube and the adsorbent case supply gas to the catalytic-adsorbent members.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: April 8, 2003
    Assignee: Korea M.A.T. Co., Ltd.
    Inventor: Dong-Soo Kim
  • Patent number: 6540467
    Abstract: A system and a method are provided for preventing damage to wafers arranged in a wafer cassette. In particular, an apparatus is provided to protect wafers arranged in a wafer cassette during insertion of a wafer into the cassette. In one embodiment, the apparatus may be a separate entity from the wafer cassette. In this manner, the apparatus may be situated about the cassette such that the wafers arranged in the cassette are protected during insertion of a wafer. In another embodiment, the wafer cassette itself may be adapted to partially cover and protect the wafers arranged in the cassette during insertion of a wafer. Consequently, a method is provided using either embodiment of the apparatus. In particular, the method may include inserting a wafer into a wafer cassette by shielding one or more slots of the cassette, exposing a designated slot of the cassette, and inserting a wafer into the designated slot.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: April 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Nael O. Zohni, Clifford Fishley
  • Patent number: 6536528
    Abstract: A system for producing hydrocarbons from a subsea well comprises an unmanned floating platform positioned over the well, the platform including equipment for inserting coiled tubing or wireline tools or the like into the well for servicing, controlling, or conducting other operations in or to the well, a vertical access riser connecting the platform to the well, a control umbilical connecting the platform to the well, a host facility adapted to receive the produced hydrocarbons, and aproduction pipeline connecting the well to the host facility, the production pipeline including at least one access port between the well and the host facility.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: March 25, 2003
    Assignee: Kellogg Brown & Root, Inc.
    Inventors: Raj M. Amin, Andrea Mangiavacchi, Nicolaas Vandenworm, James F. O'Sullivan, Clyde E. Nolan, Jr.
  • Patent number: 6534805
    Abstract: An embodiment of a memory cell includes a series of four substantially oblong parallel active regions, arranged side-by-side such that the inner active regions of the series include source/drain regions for p-channel transistors, and the outer active regions include source/drain regions for n-channel transistors. Another embodiment of the memory cell includes six transistors having gates substantially parallel to one another, where three of the gates are arranged along a first axis and the other three gates are arranged along a second axis parallel to the first axis. In another embodiment, the memory cell may include substantially oblong active regions arranged substantially in parallel with one another, with substantially oblong local interconnects arranged above and substantially perpendicular to the active regions.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: March 18, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventor: Bo Jin
  • Patent number: 6534378
    Abstract: The present invention advantageously provides a method for retaining a substantially transparent dielectric above alignment marks during polishing of the dielectric to ensure that the alignment marks are preserved for subsequent processing steps. According to an embodiment, alignment marks are etched into a semiconductor substrate. Thereafter, a pad oxide layer is deposited across the substrate surface, followed by the deposition of a first nitride layer. Isolation trenches which are deeper than the alignment mark trenches are formed spaced distances apart within the substrate. Optical lithography may be used to define the regions of the first nitride layer, the pad oxide layer, and the substrate to be etched. The isolation trenches thus become the only areas of the substrate not covered by the pad oxide layer and the first nitride layer. A substantially transparent dielectric, e.g., oxide, is then deposited across the semiconductor topography to a level spaced above the first nitride layer.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: March 18, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Krishnaswamy Ramkumar, Chidambaram G. Kallingal, Sriram Madhavan
  • Patent number: 6531553
    Abstract: This invention relates to a conventional supported heterogeneous Ziegler-Natta catalyst for the polymerization of olefins. It has been found that adding a lithium compound to a transition metal catalyst component and then adding an organoaluminum co-catalyst and an organosilicon electron donor produces a catalyst which yields polymer with increased molecular weight. The lithium compound is of the general formula LiCp wherein Cp is a cyclopentadienyl or substituted cyclopentadienyl and is preferably lithium cyclopentadienide or lithium indene. Preferably, the molar ratio of lithium compound/transition metal is at least 0.2.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 11, 2003
    Assignee: Fina Technology, Inc.
    Inventors: Edwar Shoukri Shamshoum, Christopher Bauch
  • Patent number: 6532585
    Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: March 11, 2003
    Assignee: LSI Logic Corporation
    Inventors: Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
  • Patent number: 6532439
    Abstract: A method for determining the desired decoupling components for stabilizing the electrical impedance in the power distribution system of an electrical interconnecting apparatus, including a method for measuring the ESR for an electrical device, a method for determining a number of desired decoupling components for a power distribution system, and a method for placing the desired decoupling components in the power distribution system. The method creates a model of the power distribution system based upon an M×N grid for both the power plane and the ground plane. The model receives input from a user and from a database of various characteristics for a plurality of decoupling components. The method determines a target impedance over a desired frequency range. The method selects decoupling components. The method determines a number for each of the decoupling components chosen. The method places current sources in the model at spatial locations corresponding to physical locations of active components.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: March 11, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Raymond E. Anderson, Larry D. Smith, Tanmoy Roy
  • Patent number: 6531364
    Abstract: A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: March 11, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Jr., Charles E. May
  • Patent number: 6528955
    Abstract: A flasher ballast system includes a high frequency instant start ballast and one or more transformers. The high frequency instant start ballast may provide the strike voltage and perform the current limiting functions for a fluorescent lamp. The transformers may be electrically coupled to one or both of the filaments of a fluorescent lamp to provide a low voltage to the filaments.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: March 4, 2003
    Assignee: Q2100, Inc.
    Inventors: Galen R. Powers, Mathew C. Lattis
  • Patent number: 6526637
    Abstract: A device for continuous production of foil expanded metal comprising a cutting unit for continuous production of parallel, staggered longitudinal cuts in the foil, and an expansion unit for expanding the foil with the cuts perpendicularly to the longitudinal direction of the foil, the expansion unit provided with toothed belts which grasp both edges of the foil, in addition to a running body which is arranged therebetween to expand the foil running thereon. The configuration of the device is such that a toothed belt and a toothed wheel interacting therewith at a given angle are assigned to each foil edge, the edge of the foil is grasped between the toothed belt and the toothed wheel within an input and an output point. The toothed wheels are inclined in relation to each other so that their distance perpendicular to the longitudinal direction of the foil increases at the contact angle in the longitudinal direction of the foil.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: March 4, 2003
    Inventor: Norbert Geissler
  • Patent number: 6525930
    Abstract: A carriage, provided with a mounting for one or more media devices is slideably mountable in a system unit (for example a computer system unit) such that the carriage may be slid out of an aperture the system unit. The slideable carriage means that the system unit does not need to be opened in order to insert, remove, or replace a media drive. For example, a media drive can be removed from the system unit by sliding the carriage out of the system unit, disconnecting cables from the media drive and the removing the media drive from the carriage. Similarly, a media drive can be installed in the system unit by mounting the media drive in the carriage, connecting cables to the media drive and reinserting the carriage within the system unit. The use of the slideable carriage is particularly useful for rack mountable systems where it is undesirable to have to remove the system unit from the racking system to insert a media drive.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: February 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Gary S. Rumney
  • Patent number: 6522277
    Abstract: A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A converter. The elements are intended to be of equal value, however, regardless of whether they are or not. A circuit is used to randomly select subsets of elements according to a bi-directional selection technique in order to effectively rending the elements or components of equal value. Associated with each component is a switch, and a subset of the plurality of components are correspondingly switched in successive order progressing in a first direction and, subsequently, in successive order progressing in a second direction opposite the first direction. Connecting components in a first direction from left-to-right follows by selecting components in a second direction from right-to-left, and then again selecting components in the first direction from left-to-right, and so forth.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: February 18, 2003
    Assignees: Asahi Kasei Microsystems, Inc., Broadcom Corporation
    Inventors: Ichiro Fujimori, Armond Hairapetian, Lorenzo Longo
  • Patent number: 6522776
    Abstract: A method, system, and storage medium for determining retide tilt in a lithographic system is provided. Test patterns contained on a reticle are printed in a photoresist located on an upper surface of a semiconductor substrate by a lithographic system. The test patterns may include three posts of different diameters wherein one of the diameters is approximately equal to the minimum allowable feature size printable by the lithographic system. Images of the test patterns are measured by a scanning electron microscope under the control of a computer system. The computer system then assesses the measured images of the test patterns to determine if the reticle tilt is acceptable or unacceptable. In one embodiment, the computer system may assess the measured images by comparing the measured images to predetermined images of the test patterns for different focus conditions. The computer system may also calculate the amount of reticle tilt.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: February 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Edward E. Ehrichs
  • Patent number: 6522662
    Abstract: A device for seamlessly providing 10BASE-T compatible data communications over an ordinary single twisted pair home phone line between multiple computers, between computers and peripherals, and between multiple peripherals. Each component that is to communicate over the home phone line will have a 10BASE-T compatible network interface card (NIC) for interfacing with the device. A transmit/receive switch is used to switch the device between a transmit mode and a receive mode. When signal are being transmitted from a component a Manchester coder decodes signals received from the NIC. A differential converter is used to convert the differential signal received from the NIC to a single signal. A modulator is used to modulate the signal to a RF signal using a modulation scheme such as PSK, QPSK, QAM or MCM schemes. A filter is used to limit the bandwidth of the modulated signal and a driver is used to amplify the signal to match the impedance of the phone line.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: February 18, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Ce Richard Liu
  • Patent number: 6522938
    Abstract: A system and storage medium for tracking quartzware utilization in vertical furnaces is provided. The system includes a computer server and a plurality of computer systems. The computer server maintains a database of quartzware inventory data and furnace data. The quartzware inventory data includes all relevant information about each piece of quartzware including a history of each piece of quartzware. The furnace data includes information about the part numbers of each piece of quartzware used for each vertical furnace. Program instructions are also stored on the computer server. The program allow personnel to access and modify information maintained in the database from any one of the plurality of computer systems. During servicing of a vertical furnace, the program displays each of the quartzware pieces that need to be changed. The program may also calculate statistical information relating to quartzware usage.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: February 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Miguel E. Bosquez, Misael Pecina
  • Patent number: 6517799
    Abstract: A method for recovering small bandgap fullerenes, including metallofullerenes, from soot by passivating individual fullerenes and/or metallofullerenes to an anionic configuration. The addition of extra electrons to a metallofullerene or small bandgap fullerene breaks the interfullerene bonding in the solid material, and the resulting anions are soluble in organic electrochemical solvents. Once dissolved, the small bandgap fullerenes can be plated out or precipitated by returning them to a neutral state.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: February 11, 2003
    Assignee: TDA Research, Inc.
    Inventors: Michael D. Diener, John Michael Alford
  • Patent number: 6519704
    Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: February 11, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: David C. Liddell, Emrys J. Williams
  • Patent number: 6515632
    Abstract: An antenna includes a conductive loop with multiple feed points spaced around the loop. The loop may be opened at each feed point, thereby forming multiple loop portions. In an embodiment, the antenna may be a shielded loop antenna having multiple shielded feed lines. A kit including one or more components of such a shielded loop antenna may include a conductive structure in the form of a loop having multiple radial arms. In an embodiment of a method for forming an antenna, multiple feed points may be spaced apart around a conductive loop, and a respective feed line coupled to each of the feed points. In an embodiment, the feed lines may be shielded lines connected together at a shunt connection. The antenna may produce an isotropic radiation pattern similar to that of an electrically small antenna, but from an antenna of moderate electrical size.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: February 4, 2003
    Assignee: TDK RF Solutions
    Inventor: James S. McLean