Abstract: Porous and non-porous compositions include diamond particles, non-diamond particles, or mixtures of particles consolidated with polycrystalline diamond. The composite compositions of the present invention may be formed by a process which includes the steps of preforming the particles into a preform having a desired shape, and consolidating the preform with polycrystalline diamond. The polycrystalline diamond is preferably formed using CVD techniques including application of sufficient microwave energy to maintain the preform at a temperature of between about 670.degree. and 850.degree. C. The preform may be rotated during a portion of the deposition process.

Abstract: An interconnection matrix configured according to the present invention includes a plurality of conductors disposed on a substrate which may contain an integrated circuit. A first group of the conductors are directly connected to I/O pins provided on the substrate. A second group of the conductors are internal to the substrate. A plurality of programmable elements are disposed on the substrate and are connected between selected ones of the first and second groups of conductors. By selectively programming the antifuse elements, a user may configure the conductors into a custom interconnect pattern. Means are provided to place each conductor in the second group of internal segmented conductors at a selected voltage during programming of the interconnect architecture of the present invention. The antifuses in a selected circuit path between two I/O pads are all initially programmed at an appropriate programming voltage utilizing a low current.

Abstract: A circuit for use as a channel of a minimum selector and subtractor circuit includes a P-Channel MOS transistor having a gate connected to an input node, a source connected to the output of a current source, and a drain connected to a fixed voltage source. The source of the P-Channel transistor is connectable to a common conductive line through a first switch. The source of the P-Channel transistor is also connected to the non-inverting input of a transconductance amplifier. The inverting input of the transconductance amplifier is connected to a first plate of a capacitor. The second plate of the capacitor is connected to a fixed voltage source such as ground. The output of the transconductance amplifier is connectable to its inverting input through a second switch. The output of the transconductance amplifier forms the output of the minimum selector and subtractor circuit. A plurality of individual channel circuits may all be connected to the common conductive line.

Abstract: A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that the states of m.sub.1 and m.sub.

Abstract: An apparatus for carrying out asynchronous communication among integrated circuits for inter-chip communications includes a plurality of senders disposed on an integrated circuit. Each is associated with send-initiate circuitry to indicate a request to send the occurrence of an event. The occurrence of an event causes the sender to transition from a no-event-occurred state to an event-occurred state. An address-generating circuit for generating a unique address is associated with each sender. The send-initiate circuitry of each sender is connected to an arbiter circuit. The arbiter circuit resolves simultaneous requests to send by more than one sender and provides a send-enable signal to the winning contending sender. The send-enable signal resets the selected sender to its no-event-occurred state. The send-enable signal causes the address-generating circuit associated with the winning contending sender to generate the address of that sender and place it on an output bus along with an output-enable signal.

Abstract: An antifuse according to the present invention includes a lower electrode formed from a first metal interconnect layer in an integrated circuit or the like. The lower electrode is disposed on an insulating surface. An inter-metal dielectric including an antifuse aperture disposed there lies over the inter-metal dielectric layer. The antifuse aperture extends through the inter-metal dielectric layer and also extends completely through the lower electrode. An antifuse material is disposed in the antifuse aperture. An upper electrode formed from a first metal interconnect layer is disposed over the antifuse material.

Abstract: Apparatus and a method is disclosed for mixing animation sequences with computer graphics information for presentation on a computer display screen. The animation sequences may be stored in compressed format in a standard storage medium. An animation sequence generator retrieves these compressed animation sequences, decompresses them into pixel information, and sends them to a single line store for synchronization with the computer graphics pixel information. Pixels from the animation sequences and from the computer graphics generator are mixed, windowed and overlaid in a digital mixer. The output of the digital mixer is sent to a visual display system such as a video digital-to-analog converter driving a computer display monitor.

Abstract: A method for fabricating a printed circuit board for high pin count surface mount pin grid arrays is provided where surface mount pads for soldering a surface mount pin grid array package are isolated by solder mask layers. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.

Abstract: Apparatus for forcing a memory cell to a user-selected logic level upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V.sub.CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V.sub.CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and bit lines and V.sub.CC. During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V.sub.CC by the P-Channel pullup transistors. When V.sub.

Abstract: A method of irradiating a biological specimen with ultraviolet, in particular a polynucleotide specimen selected from DNA or RNA, or optionally a protein. In the case where the specimen is DNA or RNA, or potentially proteins, the specimen is irradiated to cross-link the specimen to a substrate. In the case where the specimen is DNA, the specimen can also be irradiated to form thymine dimers. The method uses an apparatus which permits relatively precise control of the total ultraviolet dose received by the specimen, despite any changes of ultraviolet flux from the lamps which may occur from during any one experiment, or between a number of experiments. Thus, the method allows relatively highly reproducible results to be obtained.

Abstract: A clock distribution architecture is disclosed for use in a user-programmable logic array integrated circuit comprising an array of user-programmable logic elements having inputs and outputs, at least some of the user-programmable logic elements including sequential logic elements having clock inputs, and further including a plurality of general interconnect lines which may be connected to one another and to the inputs and outputs of the logic elements. The clock distribution architecture includes at least one clock input pin on the integrated circuit, a plurality of clock distribution lines disposed in the array, at least one buffer amplifier having an input connected to the clock input pin and an output connected to at least one of the clock distribution lines. At least one inverter has an input connected to at least one of the clock distribution lines, and an output.

Abstract: A metal-to metal antifuse device is provided in a double layer metal interconnect structure. A lower electrode comprises a first multilayer metal layer interconnect disposed on an insulator. An inter-metal dielectric is disposed on the first metal layer interconnect having an antifuse via. An antifuse material layer is disposed in the antifuse via and having an upper electrode comprising a second multilayer metal layer interconnect.

Abstract: A travois assembly, comprises a load-carrying frame having a lower end and an upper end. A single wheel is rotatably mounted on said lower end of said load carrying frame. A user harness includes a single vertical frame member attached to a horizontal frame member at a lower end thereof, a back pad attached to the vertical frame member at an upper end thereof, a belt circumferentially attached to the horizontal frame member, a pair of shoulder straps each having a first end attached to the back pad and a second end attached to the horizontal frame member. The load carrying frame is attached to the user harness by a universal joint having a first end rigidly attached to the upper end of the load carrying frame and a second end attached to the vertical frame member of the user harness.

Abstract: A printed circuit board includes an array of conductive pads including component-mounting holes disposed on first and second surfaces thereon. An array of conductive attachment lands arranged in pairs of first and second attachment lands are disposed on the first and second surfaces. The first and second attachment lands are insulated from one another and separated by a distance selected to allow attachment of standard sized components therebetween on the first and second surfaces of said circuit board. First and second conductive power distribution planes are disposed on the first and second surfaces and are insulated from the conductive pads and the second attachment lands disposed thereon.

Abstract: A package for one or more integrated circuit dice which includes a spreader which provides a conventional signal path between the die and a printed circuit board to which it is demountably attached as well as an additional, more readily accessible subset of signals, preferably available through a flexible cable extending horizontally from the package. The spreader provides a first set of contacts on a first side for interface to the integrated circuit dice, a second set of contacts on a second side opposite the first side which are connected to some of the contacts of the first set of contacts for connection to the printed circuit board, and a third set of contacts on the first side along one edge thereof for engaging the flexible cable and carrying the subset of signals.

Abstract: A digital circuit simulator is provided that combines the speed of a single pass simulator with the probabalistic analysis previously available only through lengthy iteration, and that avoids the extensive reporting of false errors typical to single pass simulators. The simulator represents signal level transitions and component gate delays by probability histograms. Circuit operation is divided into events, each of which is the propagation through a single component of transitions in one or more input signals to the component. Signal propagation through a component is analyzed using component models, which are provided for a variety of basic components; more complex components are represented by decomposing them into a corresponding structure of basic components. Each event is analyzed using the histograms for the input signals and for the component gate delay.Signal conflicts due to timing problems between the various inputs to a component are identified and reported.

Abstract: A curved panic guard for use with external vertical rod exit devices has no sharp, angled or flat projecting surfaces to interfere with the passage of a wheelchair.

Abstract: A two-layer network according to the present invention is comprised of a first-layer array of electrically-adaptable synaptic elements, inter-layer connection circuitry comprised of electrically adaptable elements, and a second-layer array of electrically-adaptable synaptic elements. Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor in each electrically adaptable element, usually comprising the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. Each synaptic element in the synaptic array comprises an adaptable CMOS inverter or other amplifier circuit.