Abstract: A carrier for a laser diode bar comprises a generally rectangularly shaped block formed from a dielectric material having a high thermal conductivity. The block includes a stepped recess formed therein having a height essentially equal to one half the height of a laser diode bar to be mounted thereon. An assembly for mounting a laser diode bar comprises a pair of carriers in contact with one another and oriented such that their stepped recesses are in facing relationship to one another. A laser diode bar is positioned between the carriers in the space left by their combined stepped recesses. A plurality of assemblies may be placed in contact with or separated from one another.

Abstract: A bipolar phototransistor comprises both an integrating photosensor and a switching element. The base terminal of the bipolar phototransistor is utilized as the switch-control node for the pixel and its emitter is the output node of the integrating photosensor. A plurality of integrating photosensors may be placed in an array of rows and columns, wherein the bases of all bipolar phototransistors in a row are capacitively coupled together to a common row-select line, and the emitters of all bipolar phototransistors in a column are connected together to a column sense line. The input of a sense amplifier is connected to the sense line of each column of integrating photosensors. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input connected to the sense line. A capacitor, preferably a varactor, is also connected between the inverting input and output of the amplifying element.

Abstract: An integrated, user-programmable interconnect architecture, includes a plurality of input/output pads arranged in a matrix of rows and columns, each of the input/output pads being connected to a first one of its row neighbors and a first one of its column neighbors by a two-state programmable interconnect element in series with a first three-state programmable interconnect element having first programming characteristics. A plurality of first conductors is generally disposed in a direction parallel to the rows, each of the rows having at least one of the first conductors connected through ones of the first three-state programmable interconnect elements to selected ones of the input/output pads associated therewith, at least one of the first conductors segmented by at least one of the two-state programmable interconnect elements.

Abstract: A first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The gates of the first and second MOS transistors are connected to sources of input voltage which are of a magnitude smaller than the threshold voltages of the two MOS transistors. The first MOS transistor located next to the load is kept in saturation. A related circuit includes a first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The first MOS transistor located next to the load is kept in saturation. The gates of the first and second MOS transistors are connected to the gates of third and fourth diode-connected MOS transistors of the same conductivity type as the first and second MOS transistors. The third MOS transistor is connected between a first input current node and a fixed voltage source. The fourth MOS transistor is connected between a second input current node and a fixed voltage source.

Abstract: A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that t the states of m.sub.1 and m.sub.

Abstract: A self-contained air conditioner unit comprises an enclosure including a first intake aperture positioned to communicate with outside ambient air and a first outlet aperture positioned to communicate with a habitable space in which the air conditioner is placed, and a second intake aperture positioned to communicate with a habitable space in which the air conditioner is placed, and a second outlet aperture positioned to communicate with ambient air outside of the habitable space. A water reservoir is disposed at the bottom of the enclosure. A heat exchanger is disposed in the cabinet over the water reservoir, and comprises a plurality of vertically disposed, alternating wet air channels and dry air channels, the alternating wet air channels and dry air channels defined by substantially parallel opposing heat-transfer partitions.

Abstract: A method for programming antifuses having at least one metal electrode includes the steps of providing an antifuse programming voltage source, capable of supplying alternating positive and negative programming voltage pulses; providing a programming path from the antifuse programming voltage source to the antifuse; and providing a selected number of alternating positive and negative programming voltage pulses to the antifuse through the programming path.

Abstract: A user-programmable FPGA architecture includes a plurality of logic function circuits including inputs and outputs disposed on an integrated circuit. A plurality of input/output (I/O) modules are also disposed on the integrated circuit and each include an input buffer having an input connected to I/O pad on the integrated circuit and an output connected to an output node, and an output buffer having an input connected to an input node, an output connected to the I/O pad, and a control input connected to a control node. A general interconnect structure disposed on the integrated circuit includes a plurality of interconnect conductors which may be connected to one another, to the inputs and outputs of the logic function circuits, and to the I/O modules by programming user-programmable interconnect elements. Direct interconnections are made between the inputs of selected ones of the logic function circuits and the output nodes of selected ones of the I/O modules.

Abstract: The present invention comprises an article formed from a plurality of non-diamond particles compatible with diamond deposition preformed into a desired shape. Each of the particles has first surface regions in contact with immediately adjacent other ones of the particles, and second surface regions spaced apart from the immediately adjacent other ones of said particles to define boundaries of inter-particle voids between the immediately adjacent ones of the particles. The voids are infiltrated with high thermal conductivity CVD diamond material continuously coating the second surface regions of the particles and comprising merged growth fronts from the second surface regions of individual immediately adjacent ones of the particles into the inter-particle voids.

Abstract: According to a first aspect of the present invention, a static random access memory cell according to the present invention includes two stages. The first stage has a first P-Channel MOS transistor with its source connected to a high-voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-Channel MOS transistor is connected to a V.sub.SS power supply rail. The second stage has a second P-Channel MOS transistor with its source connected to the high-voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-Channel MOS transistor is connected to V.sub.SS.

Abstract: A printed circuit board is provided with surface mount pads for soldering a surface mount pin grid array package. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.

Abstract: An interconnection element for use in an user-configurable interconnection technology includes a normally shorted fuse element and a normally open antifuse element connected in series. The antifuse element is designed to program at a first current at a selected programming voltage. The fuse element is designed to program at a second current which exceeds the first current by a margin sufficient to prevent inadvertent programming of fuse elements during the antifuse element programming cycle. An interconnection network for use in integrated circuits and other connection networks includes a plurality of circuit nodes which may be selectively connected to one another. Each circuit node is connected to other circuit nodes using the interconnection element of the present invention which includes an antifuse element which programs at a programming voltage and a first current in series with a fuse element which programs at a second current having a magnitude larger than the first current.

Abstract: A downward compatible full-duplex 10Base-T ethernet transceiver associated with either the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the twisted pair link. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of between about 2-7 .mu.sec.

Abstract: A method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer and an upper surface of the interlayer dielectric layer so as to form a substantially planar surface comprising the upper surface of the interlayer dielectric layer, the planarizing layer, and the upper surface of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) forming a metal capping layer over the antifuse material layer; and (9) defining the antif

Abstract: In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related t

Abstract: Apparatus for terminating unused input lines in a user-programmable interconnect architecture to one of a first voltage potential and a second voltage potential comprises at least one first tie-off conductor divided into at least two first segments and insulated from and intersecting the input lines, and at least one second tie-off conductor divided into at least two second segments and insulated from and intersecting the input lines. A plurality of first termination transistors each have their drains connected to a voltage rail for the first voltage potential and their sources connected to a different one of the first segments. A plurality of second termination transistors each have their sources connected to a voltage rail for the first voltage potential and their drains connected to a different one of the second segments. A termination transistor gate line is connected to the gates of each of the first and second termination transistors.

Abstract: A continuous weight-update device for a synaptic element including at least one MOS transistor comprises a floating node having a capacitance associated therewith, the floating gate comprising at least a part of the floating node, first and second input lines, first and second error lines, an electron tunneling structure coupled to the floating node for tunneling electrons from the floating node, and an electron injecting structure coupled to the floating node for injecting electrons onto the floating node. Control circuitry is responsive to signals on the first input and error lines, for activating the electron tunneling structure, and control circuitry is responsive to signals on the second input and error lines, for activating the electron injecting structure. Circuitry is provided for driving signals onto the first and second input and error lines. Both a single synapse and an array of synapses incorporating the continuous weight-update device are also taught.

Abstract: A static random access memory cell according to the present invention comprises first and second cross-coupled inverters. The first inverter includes a first P-Channel MOS transistor having a source connected to a first power supply node, a gate, and a drain, and a first N-Channel MOS transistor having a drain connected to the drain of the first P-Channel MOS transistor and forming an output node, a gate, and a source connected to a fixed power supply potential. The second inverter includes a second P-Channel MOS transistor having a source connected to the first power supply node, a gate, and a drain, and a second N-Channel MOS transistor having a drain connected to the drain of the second P-Channel MOS transistor, a gate, and a source connected to the fixed power supply potential.

Abstract: A roll film dispenser is disclosed which utilizes a switch-retractable serrated blade to cut film being dispensed. In one embodiment of the invention, the roll film dispenser contains a roll of film which is arranged so that the end of the roll exits the dispenser through a slot at the top. Severance of the film is accomplished by tearing the sheet over the serrated blade. When not in use, the serrated blade may be manually retracted. Optionally, an acrylic sheet may be interposed between the slot and the blade to aid in stabilizing PVC-type films prior to cutting. A conforming weight is provided at the lower rear of the dispenser to resist rollover.