Abstract: A method for designing an aperiodic grating structure for mode conversion and control which is based upon an inverse scattering optimization procedure. In accordance with this method, no predetermined shape or material variation of the grating structure is assumed. A constrained domain of all surfaces and material variations is searched to find an optimum aperiodic conversion surface profile for maximum conversion efficiency into the required output mode(s) or optimum control. Accordingly, the present method results in the design of rough surfaces or non-homogeneous structures for mode conversion and control. Because this method relies on scattering produced by short, forceful field perturbations, it is possible to achieve very small conversion lengths which are much less than one grating period.

Abstract: A text image stretching system in a VGA for a plurality of text image font sizes comprises a plurality of cell line replication registers having inputs and outputs, the plurality of cell line replication registers formed into groups corresponding to one of the plurality of text image font sizes, each cell line replication register having a plurality of bits, the inputs of the plurality of cell line replication registers connected to the VGA to receive cell line replication information for storage in the plurality of cell line replication registers, a multiplexer having data inputs, first and second select inputs and a plurality of outputs, each of the data inputs connected to one of the plurality of bits of the plurality of cell line replication registers, the first and second select inputs decoded to select one bit from each of the cell line replication registers in one of the groups of the cell line replication registers to form a cell line replication code for output on the plurality of outputs, a repeat c

Abstract: A logic function module comprises a plurality of input nodes and an output node. A first control circuit has at least one input connected to one of the input nodes, a first output, and a second output which is the complement of the first output. A second control circuit has at least one input connected to one of the input nodes, a first output, and a second output which is the complement of the first output. A first switching circuit is connected between one of the input nodes and the output node and is controlled from the first output of the first control circuit the first output of the second switching circuit. A second switching circuit is connected between one of the input nodes and the output node and is controlled from the second output of the first control circuit the first output of the second switching circuit.

Abstract: A method for incremental recognition of ideographic handwriting comprises in order the steps of: (1) entering in a natural stroke order at least one stroke of an ideographic character from a coordinate entry tablet; (2) providing the at least one stroke to an incremental character recognizer, which produces a hypothesis list of at least one candidate character; (3) displaying a hypothesis list of candidate characters containing the at least one stroke; (4) selecting a correct character from among the candidate characters on the hypothesis list if it a correct character appears thereon; (5) entering in natural stroke order at least one additional stroke of the ideographic character from the coordinate entry tablet if no candidate character is a correct character; (6) providing the additional stroke(s) to the incremental character recognizer, which produces an updated hypothesis list; (7) displaying the updated hypothesis list of candidate characters containing every stroke; (8) selecting a correct character fr

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.

Abstract: The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. In the preferred embodiment of the present invention, the data signals are represented as signed 16-bit binary values in a two's compliment format. An intermediate register is used to hold the intermediate signal which is greater than 16-bits in width to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control. The program determines whether the intermediate signal is in a positive or negative overflow state.

Abstract: A three-terminal silicon MOS transistor with a time-varying transfer function is provided which may operate both as a single transistor analog learning device and as a single transistor non-volatile analog memory. The time-varying transfer function is achieved by adding or removing electrons from the fully insulated floating gate of an N-type MOS floating gate transistor. The transistor has a control gate capacitively coupled to the floating gate; it is from the perspective of this control gate that the transfer function of the transistor is modified. Electrons are removed from the floating gate via Fowler-Nordheim tunneling. Electrons are added to the floating gate via hot-electron injection.

Abstract: A proximity sensor system includes a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by digital circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed.

Abstract: A switch array decoding circuit, suitable for use in a keyboard, and method according to the present invention comprises a matrix of row lines and column lines. Switches from the array are connected between intersections of the row lines and column lines. The row lines and column lines are connected to I/O pins leading to one or more components containing the decoder circuitry. The decoder circuitry first simultaneously drives the row lines while sensing the column lines. When a switch closure is detected, the states of all column lines are simultaneously sensed. This operation determines the column position(s) of the one or more switches being closed. The column lines are then simultaneously driven while simultaneously sensing the row lines. This operation determines the row position(s) of the one or more switches being closed. The row and column drive and sense order may be reversed.

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set of bits of digital information from a first signal, selecting a second set of bits of digital information from a second signal, reading the first set of bits of signal information into a first contiguous memory space to form a first word, and then reading the second set of bits of signal information into a second contiguous memory space to forming a second word, performing a first EXCLUSIVE OR operation on the first word with the second word, performing a first logical AND operation on the first word with a mask, performing a second logical AND operation of said second word with a mask, performing a first addition operation of the results of the first logical AND operation with the results of the second logical AND operation, performing a third logical AND operation on the results of the first EXCLUSIVE OR operation with a mask word, and then performin

Abstract: A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.

Abstract: A process electrostatic discharge ("ESD") protection device is incorporated on a chip with the antifuses that it is designed to protect and is formed as close in time as possible to the deposition of the antifuse material layer (the layer being protected) so that ESD protection is available at all practical stages of processing. According to a first aspect of the invention, an ESD protection device is formed by exposing edges of an antifuse bottom electrode during the antifuse cell open mask/etch step. It is biased on during processing. A sharp corner of the electrode and a deep aspect ratio provide degrade antifuse performance for the protection cell (resulting in reduced breakdown voltage and increased leakage current) and, as designed, the protection cell will rupture before other cells because it has a lower breakdown voltage. Once the protection cell ruptures, it will continue to conduct and protect other antifuses from ESD damage.

Abstract: A method for generating code for an object-oriented processor is disclosed. An instruction table is initialized to include a plurality of instructions for an object-oriented processor, each of the plurality of instructions having a set of operands and an operand type for each of the set of operands. In addition, a weighting table is initialized to include a set of the plurality of instructions and a weight for each of the set of the plurality of instructions, the weight indicating frequency of generation for a particular instruction. A class hierarchy is created, the class hierarchy having a plurality of classes stored in a tree data structure, each of the plurality of classes having a set of fields and a set of methods, each of the plurality of classes, each of the set of fields, and each of the set of methods having object-oriented properties. Within the class hierarchy, a set of objects is randomly generated for each of the plurality of classes.

Abstract: A circuit design tool which includes (1) separating structural and functional aspects of components, so as to specify the desired functional behaviour of the component, leaving the actual gate-level design of the component to the design tool; (2) translating a model of the desired logical behaviour of a circuit into a regularized set of functional components to achieve that desired behaviour; (3) verifying structural equivalence between pairs of components; (4) a method for bit-reversing the signal flow in a component; (5) a method for performing arithmetic operations backwards from a natural order; (6) an architecture for a multiplier which is faster and more compact than known multipliers; and (7) a method of translating a logic equation into a netlist of connected logic gates.

Abstract: A non-inclusive multi-level cache memory system is optimized by removing a first cache content from a first cache, so as to provide cache space in the first cache. In response to a cache miss in the first and second caches, the removed first cache content is stored in a second cache. All cache contents that are stored in the second cache are limited to have read-only attributes so that if any copies of the cache contents in the second cache exist in the cache memory system, a processor or equivalent device must seek permission to access the location in which that copy exists, ensuring cache coherency. If the first cache content is required by a processor (e.g., when a cache hit occurs in the second cache for the first cache content), room is again made available, if required, in the first cache by selecting a second cache content from the first cache and moving it to the second cache.

Abstract: An antifuse based PROM cell design allows large currents to be sinked during cell programming to ensure low programmed resistance of the cell while using minimum-geometry select devices. This is achieved by utilizing a pseudo SCR latchup effect during programming. The regions in the semiconductor substrate forming lower antifuse electrodes for the antifuses in the PROM cells are doped at low levels with phosphorus. An antifuse layer formed from an oxide, oxide-nitride, or oxide-nitride-oxide antifuse layer, is formed over the lower antifuse electrode, and an upper antifuse electrode is formed from polysilicon. A minimum-geometry N-Channel select transistor is formed in series with the antifuse to complete the PROM cell. The drain and source diffusions of the select transistor are arsenic doped and the drain diffusion is contiguous with the lower antifuse electrode. A bit line is contacted to the upper antifuse electrode and the select transistor gate is part of a polysilicon word line.

Abstract: An analog-to-digital converter according to the present invention comprising a comparator having first and second inputs, and an output, the comparator comparing an analog input voltage at the first input to a tracking voltage at the second input to place a digital output on the comparator output in response thereto, a voltage switching matrix having an input connected to the output of the comparator and an output, an integrator having an input connected to the output of the voltage switching matrix and an output connected to the second input of the comparator to complete a feedback loop and to provide the tracking signal to the second input of the comparator, and a digital filter coupled to the output of the comparator, the digital filter to form a digital output corresponding to the analog input signal at the first input of the comparator.

Abstract: A method for handling an overflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a first word. A second plurality of signal data is packed into a second memory location so as to form a second word. A bitwise operation is then performed between the first word and the second word to produce a result. The result of the operation is then stored in a k bit memory location so as to form a third word. The third word is then shifted left (k-9) bits. A bit mask is then obtained by arithmetic shifting the third word right (k-1) bits. A logical OR operation is then performed between the bit mask and the result.

Abstract: In a video controller system including a video memory and first and second pluralities of functional circuits which access the video memory, requests for access to the video memory among more than one of the functional circuits are arbitrated by two levels of arbitration. In the first level of arbitration, a buffer in each of said first pluralities of functional circuits temporarily stores data read from or to be written to the video memory. A priority is assigned to requests for access from each of the functional circuits. A low limit and a high limit are assigned for each of the buffers. Requests for access to the video memory from all of the functional circuits are monitored. Each of the buffers is monitored to indicate whether the amount of data in each buffer is below the low limit or above the high limit. Access to the video memory is granted first to any requesting ones of the functional circuits whose buffers are below the low limit in order of the assigned priority.