Abstract: Porous and non-porous compositions include diamond particles, non-diamond particles, or mixtures of particles consolidated with polycrystalline diamond. The composite compositions of the present invention may be formed by a process which includes the steps of preforming the particles into a preform having a desired shape, and consolidating the preform with polycrystalline diamond. The polycrystalline diamond is preferably formed using CVD techniques including application of sufficient microwave energy to maintain the preform at a temperature of between about 670.degree. and 850.degree. C. The preform may be rotated during a portion of the deposition process.

Abstract: A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive.

Abstract: The present invention is directed to checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor. In the preferred embodiment of the present invention, the data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer.

Abstract: A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.

Abstract: In a 100BASE-T4 protocol network, the "carrier.sub.-- status" signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A method for handling an underflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a first word. A second plurality of signal data is packed into a second memory location so as to form a second word. A bitwise operation is then performed between the first word and the second word to produce a result. The result of the operation is then stored in a k bit memory location so as to form a third word. A bit mask is then obtained by arithmetic shifting the third word right (k-1) bits. The bit mask is then inverted. A logical AND operation is then performed between the inverted bit mask and the result.

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first signal a first plurality of bits of signal information to be processed, selecting from a second signal a second plurality of bits of signal information to be processed, reading the first plurality of bits of signal information into contiguous memory space so as to form a first word, reading the second plurality of bits of signal information into contiguous memory space so as to form a second word, causing a first logical AND operation to be performed on the second word with a mask, causing a first logical OR operation between the first word and the complement of the mask, causing a first EXCLUSIVE OR operation between the first word and the complement of the second word, causing a second logical AND operation between the results of the first EXCLUSIVE OR operation and the complement of the mask, subtracting the results of the first logical AND operati

Abstract: An adjustable hair curler includes a thin sheet of a flexible resilient material. A coating on a first side of the resilient sheet includes a soft material for contacting and gripping the hair. A coating is also applied to the second opposite side of the resilient sheet. The coatings are able to withstand repeated heat cycling. Application of heat from a heat source to the curler causes heat to flow into the curler, heating the resilient sheet and coatings. The thermal mass of these elements keeps the curler heated for some period of time after the curler is removed from the heat source. By rolling the sheet to form a cylinder so that a portion of the sheet overlaps another portion of the sheet, and clipping the two portions together with a clip such as a bobby pin or the like, the cylinder's shape may be established and held with relative ease and simple adjustability of cylinder diameter. For storage, the sheets may be completely flattened for storage or transport in a very minimal volume.

Abstract: A proximity sensor system includes a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed.

Abstract: The present invention is directed to a novel adjustable diameter hair curler which is extremely lightweight, portable, and suitable for travel. The novel adjustable curler includes a substrate of a flexible material such as a plastic or fabric or backing material which may optionally include a thin spring steel lamination for added resilience. The substrate has a first planar side and a second planar side opposite said first planar side. Attached to the first side of the substrate are an array of hook-type elements from a hook and loop-type fastening system such as VELCRO.RTM. brand hook and loop fasteners available from Velcro Industries of Manchester, N.H. The hook-type elements are generally arrayed over the majority of the first side. Strips of engaging materials are provided on each side of the substrate to secure the adjustable curler in a cylindrical form having a selected diameter.

Abstract: A method for processing data in a computer containing a processor is described, wherein the method comprises the steps of providing at least one program object having an instruction set, and at least one set of rules responsive to input data, the set of rules being used by the processor to determine program instructions to be issued, providing a form-based user interface, accepting input data from a user of a computer system through the forms-based user interface, causing the processor to compare the input data to one or more of the rules to determine at least one next program instruction to be executed, and then causing said at least one next program instruction to be executed. The forms-based user interface comprises standard Hyper-Text Markup Language constructs, together with new work flow interface commands which, depending on the information submitted to or received from the work flow process through one or more user interfaces, may alter that work flow process.

Abstract: The method and apparatus for checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. The data signals are represented as unsigned 8-bit binary values. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a maximum overflow state or a minimum overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is in the maximum or minimum overflow state.

Abstract: Security functions for a computer system are controlled by a security monitor. A user desiring access to the system inputs a user identification and password combination, and a role the user to assume is selected from among one or more roles defined in the system. Upon being validated as an authorized user performing a particular role, the user is then authorized to perform certain functions and tasks specifically and to see information associated with that role (and optimally the work group the user is assigned). For some users, no role or a "null" roll is chosen, and authorization for certain functions and tasks is accomplished due to that particular user having been predefined by an administrator as being allowed to perform those functions and tasks, usually due to the predefined privileges associated with the work group(s) to which the user belongs.

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.0E17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 um. The thickness of the third (p+) region should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.

Abstract: Methods for recognizing gestures made by a conductive object on a touch-sensor pad and for cursor motion are disclosed. Tapping, drags, pushes, extended drags and variable drags gestures are recognized by analyzing the position, pressure, and movement of the conductive object on the sensor pad during the time of a suspected gesture, and signals are sent to a host indicating the occurrence of these gestures. Signals indicating the position of a conductive object and distinguishing between the peripheral portion and an inner portion of the touch-sensor pad are also sent to the host.

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set of bits of digital information from a first signal, selecting a second set of bits of digital information from a second signal, reading the first set of bits of signal information into a first contiguous memory space to form a first word, and then reading the second set of bits of signal information into a second contiguous memory space to forming a second word, performing a first EXCLUSIVE OR operation on the first word with the second word, performing a first logical AND operation on the first word with a mask, performing a second logical AND operation of said second word with a mask, performing a first addition operation of the results of the first logical AND operation with the results of the second logical AND operation, performing a third logical AND operation on the results of the first EXCLUSIVE OR operation with a mask word, and then performin

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: An autozeroing floating-gate amplifier (AFGA) is an integrated continuous-time filter that is intrinsically autozeroing. It can achieve a highpass characteristic at frequencies well below 1 Hz. In contrast with conventional autozeroing amplifiers that eliminate their input offset, the AFGA nulls its output offset. The AFGA is a continuous-time filter; it does not require any clocking. The AFGA includes at least one floating-gate MOS transistor that is capable of hot-electron injection of electrons onto the floating gate of the MOS transistor. Electrons are continuously removed from the floating gate(s), for example, via Fowler-Nordheim tunneling. The AFGA has a stable equilibrium for which this tunneling current is balanced by an injection current of equal magnitude.

Abstract: The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. In the preferred embodiment of the present invention, the data signals are represented as signed 16-bit binary values in a two's compliment format. An intermediate register is used to hold the intermediate signal which is greater than 16-bits in width to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control. The program determines whether the intermediate signal is in a positive or negative overflow state.