Abstract: An access multiplexer (10) for a digital subscriber line (DSL) communications network, having element management system (EMS) capability, is disclosed. A host computer (17) is coupled to the DSL access multiplexer (DSLAM) (10) over a serial interface (27, 28). A controller (25) of the DSLAM includes an EMS agent (60) for receiving command control and information request messages from the host computer (17) over the serial interface (27, 28). The EMS agent (60) issues signals to a software process, such as the DSL channel manager (38c) in response to such messages, and generates replies to the host computer (17) over the serial interface (27, 28) upon execution of the requested operation. The controller (25) also operates in response to command control and information request messages initiated at user computers (U) that reside on a network (14).

Abstract: The present invention includes a method and system for routing broadcast packets in a network (250) using a switching device (200) which is operable to interconnect sub-portions (202, 204) of the network (250). Each network (250) sub-portion (202, 204) is connected to at least one of a plurality of switch ports (232, 236, 240, 244) on the switching device (200). The switching device (200) is further operable to forward certain ones of the broadcast packets between the sub-portions (202, 204) of the network (250) via the switch ports (232, 236, 240, 244) in accordance with a forwarding algorithm and to forward all other of the broadcast packets to a processor (320). The processor (320) is communicatively connected to the switching device (200) and is operable to forward the other ones of the broadcast packets in accordance with a set of pre-defined broadcast routing heuristics.

Abstract: A method and device for combating logarithmic quantization and Robbed Bit Signaling (RBS) impairments that..are typical to PCM telephone lines is descried. An apparatus is described which includes a front-end unit which receives samples of the digital PCM line, an impairment identifier unit which identifies samples that have a high likelihood to have, large impairments due to the PCM line, an impairment estimator unit which estimates the value of impairment caused by the digital line, a samples reconstructor unit which fixes received samples by subtracting from them the value of the estimated impairment and an output unit transfers the reconstructed samples to a receiver. The method allows improving signal quality at the output of the PCM line, and thus improving data rates and robustness of digital communication receivers, and particularly of V.34 receivers, or V.90 transceivers that are digitally linked to the PCM, line.

Abstract: A modem (12) including a least-significant bit convolutional coding scheme is disclosed. In the transmit side of the modem (12), an encoder (28) is included, within which convolutional coders (35I, 35Q) are used to each encode one bit of each symbol applied to a phase and amplitude modulation constellation, preferably the least significant bits, such that the encoded bits select one of a plurality of sub-constellations in the modulated signal. Each of the coders (35, 35′) are arranged as finite state machines, of either thirty-two or sixty-four states. The minimum Hamming distance (dfree) provided by the codes is four, such that the resulting coding gain of the modem is improved over conventional encoding schemes.

Abstract: A process-insensitive, highly-linear, constant transconductance circuit employs a CMOS multiplier in the signal path that is offset biased with a specific combination of currents to compensate for variations in transconductance due to resistor processing variations.

Abstract: The present invention provides for a statistics Cyclic Redundancy Check (CRC) (108) wherein the statistics CRC (108) is representative of the values contained within a statistics RAM (110). The statistics CRC (108) is then used to reduce test vectors by allowing the validity of the statistics to be determined by reading this signature instead of reading all the individual statistics. The signature is regenerated for each complete pass of the statistics, and the contents of this register are only updated when the pass is complete.

Abstract: A system and method for interworking a net communication beginning with a proxy protocol and allowing retention of the fullest feature set for enhanced communications between devices. The system within a communications network, receives and analysis the protocol capabilities received by components attempting to establish a communications link and establishes a new proxy protocol based upon commonality of features.

Abstract: For PCM upstream, the analog modem must transmit a filtered sequence of symbols so that the samples of the signal at the input to the codec at the central office (CO) are at a predetermined set of levels. This requires that the analog modem use an 8 kHz symbol rate synchronized to the CO clock. Typical telephone channels have nulls at DC and at 4 kHz. Therefore, for best performance, the signal transmitted by the analog modem should be spectrally shaped to match the channel. The present invention utilizes a generalized Laroia-Tretter-Farvardin (LTF) precoder similar to the one used in V.34. This precoder structure allows spectral shaping and could also allow for constellation shaping gains. Using this precoder structure with spectral shaping has the potential to improve data rates by 3-3.5 kbps.

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: An electronic system (100) includes a register (TONTOFF) for data and a clock circuit (2340, 708) coupled to the register and responsive to the data in the register to generate a series of clock pulses (CPU.sub.-- CLK). The series of clock pulses occupies time intervals (2550) interspersed with time intervals free of clock pulses (2552), as an output having a ratio of the time intervals responsive to the data. Other devices, systems and methods are also disclosed.

Abstract: Objective: To make it possible to easily increase the integration level and increase the memory capacity of a semiconductor memory device by using a single redundant decoder to completely repair defects at one or two neighboring addresses. Structure: The redundant circuit of the present invention comprises the following: an address code conversion circuit (2) which converts address signals, inputted in binary code, into gray code; a decoder (3) which outputs a coincidence signal after determining whether the addresses set in advance coincide or do not coincide with the gray code outputted from the aforementioned address code conversion circuit; a first driver (DR2) which drives a first redundant line which is connected to a redundant memory cell designed to supplement memory cells in which defects have occurred; and a second driver (DR1) which drives a second redundant line.

Abstract: A computer system (6) includes a printed circuit board (302), a microprocessor chip (102), a peripheral unit chip (110), a card interface chip (112), and a display controller chip (114) mounted on the printed circuit board (302) at vertices of a quadrilateral (303). A clock buffer chip (180) is mounted on the printed circuit board (302) in the interior of the quadrilateral (303) and connected to each of the microprocessor chip (102), peripheral unit chip (110), card interface chip (112), and display controller chip (114). Other circuits, systems, and methods are disclosed.

Abstract: A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) to the microcomputer integrated circuit (102) and has a second power management circuit logic (1620, 1630) that responds to a plurality of interrupt event inputs (in CSC REGs A, B) and concentrates these inputs to a single card system management interrupt output (CRDSMI#). A peripheral processor integrated circuit (110) has a third power management circuit (920) including a plurality of system management interrupt (SMI) sources, and a SMI unit (2370). The SMI unit (2370) has an output (SMI#) connected to the SMI input of the microprocessor integrated circuit. The SMI unit (2370) responds to the card SMI output of the card interface integrated circuit (112) as well as the plurality of SMI sources.

Abstract: An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5). A first inverter (5526) is connected between first supply voltage (3.3v) and ground and has a first inverter input (IN) and a first inverter output. A second inverter (5518) is connected between second supply voltage (5v) and ground and has a second inverter input (INT) and a second inverter output (OUT). A first feedback transistor (5520) has connections to the second supply voltage (5v), and to the second inverter input (INT) and the second inverter output (OUT). A second feedback transistor (5524) has connections to ground, and to the second inverter input (INT) and the second inverter output (OUT). First and second open-type inverters (5522, 5528) are connected to ground and each of the open-type inverters has an input and output.

Abstract: A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) to the microcomputer integrated circuit (102) and has a second power management circuit logic (1620, 1630) that responds to a plurality of interrupt event inputs (in CSC REGs A, B) and concentrates these inputs to a single card system management interrupt output (CRDSMI#). A peripheral processor integrated circuit (110) has a third power management circuit (920) including a plurality of system management interrupt (SMI) sources, and a SMI unit (2370). The SMI unit (2370) has an output (SMI#) connected to the SMI input of the microprocessor integrated circuit. The SMI unit (2370) responds to the card SMI output of the card interface integrated circuit (112) as well as the plurality of SMI sources.

Abstract: A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

Abstract: A computer system (6,7) includes first and second I/O circuits (932, 934), 51, 97 first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), 51, 97 a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an related information between the DMA controller and a requesting device in the docking station. Other devices, systems and methods are also disclosed.

Abstract: A computer system has an integrated circuit including a single-chip integrated circuit including an external-to-internal bus interface circuit coupled to external pins for connection to an external bus, and an on-chip internal bus coupled to the external-to-internal bus interface circuit and having a plurality of at-least-sixteen bit data paths including first and second such data paths. A parallel port on-chip is coupled to the on-chip internal bus and to both the first and second data paths therein. An interface circuit is coupled between the first and second data paths, wherein the first data path is connected to reflect the state of external inputs to the on-chip internal bus and of any internally generated second data path outputs to be sent externally, and wherein when the second data path carries internally generated signals to internal destinations, the states of the first and second data paths differ. Other circuits, systems and methods are also disclosed.

Abstract: A method and circuitry for testing a memory to determine its column address organization are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes a controllable multiplexer that selects certain combinations of address bits for use as column address bits to be applied to the memory; the selection of the multiplexer is controlled by the contents of a memory array type register associated with the memory or memory bank. In operation, a first data word is written to memory using a first address, and a second data word is written to memory using a second address that is spaced apart from the first address by a specified increment related to a trial number of column address bits of the memory.

Abstract: A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit.