Abstract: An electronic device (PPU 110) includes a data source (7201) supplying data and successive control signals indicative of valid-data, wherein transitions occur in the data during intervals between the signals indicative of valid-data, and a selector (7205) having a first input connected to the data source (7201), and a second input (7214), and an output. A circuit (7207) is connected to the output of the selector (7205) to receive data from the data source (7201) via the selector (7205). A source of a quieting signal (7220) is connected to the second input (7214), and the selector (7205) is responsive to the control signals (7206) to select the quieting signal (7220) during at least a portion of the interval between the signals indicative of valid data, and to select the data source in response to at least some of the successive control signals indicative of valid-data. Other devices, systems and methods are also described.

Abstract: This is a device package comprising: a leadframe comprising a plurality of leads for effecting circuit connections to the device; and a metal ground piece connected to the leadframe. Other devices and methods are also disclosed.

Abstract: Generally and in one form of the invention this is a periodic surface filter comprising at least one element at a surface of the filter and electronic controls to change the optical characteristics of the element. Other methods and devices are disclosed.

Abstract: Generally and in one form of the invention this is a periodic surface filter comprising at least one element at a surface of the filter and electronic controls to change the optical characteristics of the element. The surface filter is used as a switchable filter in a cavity for a Q-switch.

Abstract: Generally and in one form of the invention this is a periodic surface filter comprising at least one element at a surface of the filter and electronic controls to change the optical characteristics of the element. The surface filter comprising and electronically tunable electro-optic material to alter the resonant frequency of the element.

Abstract: Generally and in one form of the invention this is a periodic surface filter comprising at least one element at a surface of the filter and electronic controls to change the optical characteristics of the element. Other methods and devices are disclosed.

Abstract: A bistable deformable mirror device (DMD) pixel architecture is disclosed, wherein the torsion hinges are placed in a layer different from the torsion beam layer. This results in pixels which can be scaled to smaller dimensions while at the same time maintaining a large fractional active area, an important consideration for bright, high-density displays such as are used in high-definition television applications.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: This is a programmable processing system which comprises: one or more computer networks each of the networks has at least one population of processor nodes; at least one population of storage nodes; and at least one switch to provide transfer of information between the processor nodes and the storage nodes. Each processor node has at least one processing module comprising spatial light modulators; processors; and at least one hologram. Other methods and devices are disclosed.

Abstract: A circuit arrangement for gate-controlling a MOS field-effect transistor (T.sub.o) comprises a discharge circuit (12) via which the charge stored in the gate-source capacitance (C.sub.GS) can be discharged according to a time constant, the value of which depends on the internal impedance of said discharge circuit (12). This discharge circuit (12) can be switched between two conditions determined by a relatively large and a relatively small internal impedance respectively and assumes the condition dictated by the relatively small internal impedance as soon as the gate-source voltage (U.sub.GS) has dropped below a predetermined limit.

Abstract: An apparatus (38) for storing data includes a storage media (14). Also included are a number of vertical bars (40), each providing a vertical edge (50) for defining columns (44), and a number of horizontal bars (42), each providing a horizontal edge (52) for defining rows (46). The vertical bars (40) and the horizontal bars (42) are printed on storage media (14). A number of data blocks (48) are formed, each data block (48) located in a row (46), column (44) position.

Abstract: This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substrate 10, a buffer layer 12 over the substrate 10, and a channel layer 14 over the buffer layer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

Abstract: To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source +Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . . OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . . SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.

Abstract: This is a vertical MOSFET device with low gate to source overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, a gate electrode 36 surrounding the vertical pillar, and an insulating spacer 38 between the source 24,26 and a portion of the gate 36 regions.

Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: An apparatus (38) for storing data includes a storage media (14). Also included are a number of vertical bars (40), each providing a vertical edge (50) for defining columns (44), and a number of horizontal bars (42), each providing a horizontal edge (52) for defining rows (46). The vertical bars (40) and the horizontal bars (42) are printed on storage media (14). A number of data blocks (48) are formed, each data block (48) located in a row (46), column (44) position.

Abstract: Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.

Abstract: A constant-voltage circuit which can be driven by a low voltage (lower than 1 V) of a nickel-cadmium battery, etc., and which provides a temperature-compensated stable voltage output. The constant-voltage circuit comprises battery 1, band-gap-type current-mirror-type constant-current source circuit 3 which outputs collector current I.sub.C9 of transistor Q.sub.9 with a positive temperature coefficient, current source circuit 5 which outputs collector current I.sub.C8 of transistor Q.sub.8 having a negative temperature coefficient and defined by base-emitter voltage V.sub.BEQ7 of transistor Q.sub.7, and a load resistor element R.sub.0. At node N.sub.0, collector current I.sub.C9 and collector current I.sub.C8 are added. The temperature coefficients of these two currents cancel each other. Consequently, the current at node N.sub.0 does not have temperature dependence. Load resistor element R.sub.0 converts this current to a voltage as the output voltage V.sub.OUT.

Abstract: A high-speed decoder for salvaging defective memory cells which has voltage generators VG0 and VG3 for generating voltages having binary logic levels corresponding to the bit information of each column of the addresses of defective memory cells. Upon input of a memory address signal, the voltage level of the bits of each column of the address signal are checked against the voltage levels corresponding to each column from the voltage generator. When all of the columns agree, an address agreement signal is generated by an address corroboration circuit including exclusive OR gates EX0 to EX3 and a NAND gate 10.