Abstract: This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substance 10, a buffer layer layer 12 over the substrate 10, and a channel layer 14 over the buffer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.

Abstract: To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source+Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . .OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . .SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.

Abstract: A method of resetting coupled modules and a system using the method are disclosed. The method comprises applying a reset instruction signal to a selected module, the selected module generating a reset permission request signal, one or more other modules (other than the selected module) receiving the reset permission request signal and taking necessary action to avoid system malfunction after the selected module is reset, the one or more other modules sending a permission granted signal, and resetting the selected module once it is determined that the one or more modules have sent a permission granted signal. Other methods and systems are disclosed.

Abstract: A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anisotropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

Abstract: This is a method for forming patterned features. The method comprises: forming a single layer of resist 12 on a substrate 10, the layer 12 having a thickness; patterning the resist by selective exposure to a first energy source 16 to modify the developing properties of portions of the resist, leaving an amount of the thickness unexposed; and developing the resist. This is also a device which comprises: a substrate; a layer of resist over the substrate; and an energy absorbing dye in the resist. Other methods and structures are also disclosed.

Abstract: This is a package [10] for an rf device [11] operable with a characteristic impedance providing a plurality of terminals [12-19] and [101] for effecting circuit connections to the device, the connection between at least one of the terminals and the device being matched in relation to the characteristic impedance. Other devices and methods are also disclosed.

Abstract: This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropically etching the bonding layer forming chambers in the bonding layer; stacking the first and second wafers with the metal against the second wafer's bonding layer; forming a chemical bond between the metal layer and the bonding layer (e.g. between the titanium 20 and the poly 38) in a vacuum chamber, thereby creating micro-vacuum chambers (42) between the wafers; selectively etching the second wafer to form a thin semiconductor layer ( e.g. epi layer 30). This is also a semiconductor-on-insulator wafer. The wafer comprises: a substrate (e.g. semiconductor substrate 20); a layer of metal (e.g. titanium 24) and semiconductor ( e.g. silicide 40) over the substrate; a bonding layer (e.g.

Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.

Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.

Abstract: This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50,52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 , over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

Abstract: Generally, and in one form of the invention a semiconductor device is presented comprising: a transistor comprising an emitter finger and a base finger; and a ballast impedance connected to the base finger. Other devices and methods are also disclosed.

Abstract: This is a method of forming a semiconductor-on-insulator water with a single-crystal semiconductor substrate.

Abstract: This is a FET device and the device comprises: a buffer layer 30; a channel layer 32 of doped narrow bandgap material over the buffer layer; and a resistive layer 34 of low doped wide bandgap material over the channel layer, the doping of the channel layer and the resistive layer being such that no significant transfer of electrons occurs between the resistive layer and the channel layer. This is also a method of making a FET device.

Abstract: This is method for forming epitaxial structures on a substrate which comprises: forming a first epi layer on the substrate; removing one or more substantial portions of the first epi layer; forming a second epi layer over the first epi layer and adjacent said first epi layer; forming a masking layer over portions of the second epi layer which are not over the first epi layer; and substantially removing a portion of the second epi layer which is over the first epi layer to provide a substantially planar structure having different properties. Other devices and methods are also disclosed.

Abstract: This is a board to transport and convert optical outgoing free-space signals from a spatial light modulator which comprises: at least one detector to process the outgoing free-space signal; at least one signal transmitter to process the outgoing free-space signal; and at least one outgoing optical signal carrier to carry a converted outgoing signal. Other methods and devices are disclosed.

Abstract: Resist (402) is exposed by a beam of positrons (320) in an apparatus (300) similar to an electron beam lithography machine.

Abstract: A method and apparatus for performing free space optical interconnection. A micro-mirror type of spatial light modulator has an array of mirror elements, whose height with respect to a deflection plane can be individually adjusted. These heights are adjusted such that an input beam of light is phase modulated, and by interference, it is deflected to a desired detector. More than one input beam can be used with the same spatial light modulator, whose mirror elements are adjusted in patterns for deflecting and focussing to multiple detectors.

Abstract: This is a crossbar switch which comprises: X rows by Y columns of modular optical switches each comprising X or more channel inputs and X or more channel outputs where X is greater than one; and each of columns 1 to Y-1 of the modular optical switches having 1/Xth of the channel outputs optically connected to 1/Xth of the channel inputs of each of the modular optical switches in a next column. Other methods and devices are disclosed.

Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.