Abstract: This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

Abstract: DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructure on top of an underlying CMOS address circuit. The CMOS chip surface contains several processing artifacts that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.

Abstract: A high speed, low power parallel analog-to-digital converter (100) with comparator (C.sub.j) having sense amplifiers operating with low power, high speed and a ROM encoder (130) also operating in low power, high speed regime.

Abstract: Resist (402) is exposed by a beam of positrons (320) is an apparatus (300) similar to an electron beam lithography machine.

Abstract: An electrostatically deflectable beam spatial light modulator with the beam composed of two layers of aluminum alloy and the hinge connecting the beam to the remainder of the alloy formed in only one of the two layers; this provides a thick stiff beam and a thin compliant hinge. The alloy is on a spacer made of photoresist which in turn is on a semiconductor substrate. The substrate contains addressing circuitry in a preferred embodiment.

Abstract: This is an optical interconnect system. The system comprises: at least one signal transmitter; at least two signal receivers; at least one DMD in the same plane as the signal transmitter; and a hologram, whereby the phase of the original beam from the signal transmitter may be programmably changed, by a DMD, such that the beams received at the signal receiver may cancel or reinforce. Other methods and devices are disclosed.

Abstract: This is a monolithic PIN diode switch circuit. The switch comprises: input ports, output ports, bias nodes and PIN diodes. Each port or node is connected to receive a bias signal. Preferably the PIN diodes are fabricated from GaAs or other III-V compound. This monolithic PIN diode switch offers broader band performance and smaller size. Other methods and devices are disclosed.

Abstract: This is a monolithic PIN diode switch circuit. The switch comprises: input ports, output ports, bias nodes and PIN diodes. Each port or node is connected to receive a bias signal. Preferably the PIN diodes are fabricated from GaAs or other III-V compounds. This monolithic PIN diode switch offers broader band performance and smaller size. Other methods and devices are disclosed.

Abstract: This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

Abstract: This is a method of forming a semiconductor-on-insulator wafer with a single-crystal semiconductor substrate.

Abstract: This is a p-n junction device and the device comprises: a substrate 10 composed of a semiconductor material; a heavily doped n type sub-collector layer 14 over the substrate; a n type collector layer 16 over the sub-collector layer; a heavily doped p type first base layer 18, over the collector layer; a p type second base layer 20, substantially thinner than the first base layer, over the first base layer, with the second base layer being less heavily doped than the first base layer; and a n type emitter layer 24 over the second base layer, whereby, the second base layer serves as a diffusion barrier between the base and the emitter. Other devices and methods are also disclosed.

Abstract: Methods, and products formed by such methods, of forming a self-aligned conductive pillar (16) on an interconnect (12) on a body (10) having semiconducting surfaces. A first mask (24) defines an inverse pattern for formation of an interconnect (12). The interconnect (12) is formed by additive metallization processes. A second mask (26) is formed over portions of the first mask (24) and the interconnect (12). Sidewalls of the first mask (24) which define at least one side of side of said interconnect (12) serve to also define at least one side of said conductive pillar (16). The second mask (26) also defines at least one side of the conductive pillar (16). The conductive pillar (16) is formed by additive metal deposition processes. The conductive pillar (16) is thus self-aligned to the interconnect (12) on which it is formed.