Abstract: An electronic device battery pack for a battery requiring cycling to prolong lifetime is divided into at least two parallel cells for which the charging state is automatically maintained. When external power is available and one or more cells is substantially discharged, the substantially discharged cell(s) are selected one at a time to be fully drained and recharged. A partially discharged but not substantially discharged cell will be left in that state until use of the electronic device has substantially discharged the cell. Once a cell has been recharged, the next substantially discharged cell is drained and recharged, and so on until all cells are fully charged. If the charging of a cell is interrupted by removal of the external power, another cell is utilized to provide power to the electronic device and recharging is resumed once the external power is restored.

Abstract: A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The deposition step is periodically interrupted.

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage.

Abstract: A tungsten film stack is formed on a wafer using a deposition chamber by first depositing a nucleation on the wafer in the presence of a carrier gas, such as nitrogen. Following deposition of the nucleation, excess carrier gas is evacuated from the deposition chamber. Then, following evacuation of the excess carrier gas, a tungsten fill is deposited over the nucleation.

Abstract: A design for an overvoltage protection circuit can be used to fabricate several different circuits incorporating different protection techniques. The design is suitable for use in a single device, which can be easily and inexpensively packaged and protected from the environment. Three terminal protection circuits can have three terminals on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular design. Additional circuitry can be included to sense for high current conditions which are caused by overvoltages too low to trigger the normal overvoltage protection circuits.

Abstract: Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: An end-of-charge detection technique for a battery charger is described. The technique involves the detection of a voltage drop at the end of charging and eliminates the effect of noise spikes.

Abstract: An end-of-charge detection technique for a battery charger is described. The technique involves the detection of a voltage drop at the end of charging and eliminates the effect of noise spikes.

Abstract: A cut through is provided in a combined router/switch in a data processing system network by having the router store and forward a first portion of a data flow from a source to a destination. The router determines whether the data flow is suitable for cut through. If found suitable, the router sends a redirect protocol to the source, directing the source to use a different destination address for all or part of the remainder of the data flow. The portion of the data flow having new destination address is then cut through the combined router/switch by the switch. If the cut through has a failure, responsibility for the data flow delivery returns to the router. If the destination of a cut through data flow is unavailable, the frames are stored by the switch and forwarded when the destination is available.

Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.

Abstract: Accurate calculation of the probability of outage for a cell within a CDMA network is utilized to relate cell coverage to cell capacity. Based on a desired probability of outage, the coverage of the cell may be calculated for an average number of users within the cell. The calculation is independent of the admission policy employed to achieve the specified average number of users. The resulting closed form expression for the tradeoff between coverage and carried traffic allows an optimal design of a CDMA network.

Abstract: For scripting objects in a component software architecture, a generic IDE interface to scripting IDEs is defined to allow connection to a language-specific scripting IDE preferred by a user. IDE class information--methods, properties, and events, including callback methods--for IDE editable objects are saved with an IDE instance of the IDE editable objects corresponding to objects registered for scripting. The IDE instance and its handle are connected to a scripting component through a corresponding Java object and handle. Language-specific scripting IDEs may thus be connected to a scripting component for a different language-specific scripting engine. Any scripting IDE may therefore be utilized for creation and execution of scripts written in a specific language for any scripting engine, allowing the user to employ a preferred scripting IDE regardless of the scripting language selected to connect registered objects.

Abstract: A high performance file system (HPFS) is validated by checking the directory entries to the extent possible, saving the information required to check F-Nodes and queuing detected errors together with corrective actions. The F-Nodes are then checked in order, minimizing the head motion required to read the F-Nodes and also reducing the I/O time required for the validation process. The detected errors may then be processed, corrective action taken, and the affected DIRBLK written. To reduce the amount of memory required, the directory structure of an HPFS storage device may be processed employing a breadth-first, level-by-level approach. Checking of the directory entries may be further segmented into multiple threads to take advantage of the ability of RAID systems to issue multiple read requests.

Abstract: A pragma is defined to indicate straight path optimization for compilers (SPOC). The pragma is inserted into source code to identify the most common case for a branch point in a program flow, determined by analysis of performance data or simple prediction. The compiler employs this information to optimize the common case as a straight path through the function assembler code, removing unnecessary jumps and the nonoptimized case from the function body. The resulting executable code is more compact and executes faster.

Abstract: A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation enters the initiating device's architected logic queue to be issued on the system bus. The flag remains set even after the architected logic queue is drained, and is reset only when a synchronization instruction is received from a local processor, providing historical information regarding architected operations which may be pending in other devices. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered. When a local processor issues a synchronization instruction to the device managing the architected logic queue, the instruction is generally accepted when the architected logic queue is empty.

Abstract: Cache and architectural functions within a cache controller are layered so that architectural operations may be symmetrically treated regardless of whether initiated by a local processor or by a horizontal processor. The same cache controller logic which handles architectural operations initiated by a horizontal device also handles architectural operations initiated by a local processor. Architectural operations initiated by a local processor are passed to the system bus and self-snooped by the controller. If necessary, the architectural controller changes the operation protocol to conform to the system bus architecture.

Abstract: Cache and architectural specific functions are layered within a controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable.

Abstract: A method and apparatus in a wireless communications system for presenting a calling party name to a mobile station within the wireless communications system. A communications signal is received from a network to initiate a call to a mobile station within the wireless communications system. Next, a determination is made as to whether the mobile station is provisioned to receive calling party names in response to receiving the communications signal. A calling party name is either identified using a database located within the wireless communications system or the calling party name is received as part of the initial call setup signal. Then, the calling party name is sent to the mobile station over the air interface in response to identifying the calling party name.

Abstract: Cache and architectural specific functions within a cache controller are layered and provided with generic interfaces, isolating the complexities of each and allowing the overall functionality to be further divided into distinct, largely autonomous functional units. Each functional unit handles a certain type of operation and may be easily replicated or removed from the design to provide a number of cache designs with varied price and performance.