Abstract: A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter the register contents whenever an event to be counted occurs. The bit positions for generating the input are selected to produce the longest sequence of nonrepeating patterns possible. The event counter may be implemented in a small area, allowing a large number of event counters to be implemented in an array like structure within a single device and to operate as extremely high frequencies.
Type:
Grant
Filed:
April 14, 1997
Date of Patent:
August 4, 1998
Assignee:
International Business Machines Corporation
Abstract: A PCI local processing system is operated at 50 MHz using 5 V connectors for add-in boards and a 5 V signaling environment with an appropriate timing budget. Only the 5 V add-in boards may be used for 50 MHz adapters installed in the bus. The bus is backward compatible with existing 33 MHz PCI specifications and operates at 33 MHz if a 33 MHz adapter is installed, and will operate at 50 MHz if only 50 MHz adapters and/or 66 MHz adapters which utilize the universal boards are installed.
Type:
Grant
Filed:
December 13, 1996
Date of Patent:
June 30, 1998
Assignee:
International Business Machines Corporation
Abstract: The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.
Type:
Grant
Filed:
August 12, 1996
Date of Patent:
June 9, 1998
Assignee:
International Business Machines Corporation
Inventors:
James Allan Kahle, Chin-Cheng Kau, Aubrey Deene Ogden, Ali Asghar Poursepanj, Paul Kang-Guo Tu, Donald Emil Waldecker
Abstract: A method and system for detecting authorized programs within a data processing system. The present invention creates a validation structure for validating a program. The validation structure is embedded in the program and in response to an initiation of the program, a determination is made as to whether the program is an authorized program. The determination is made using the validation structure.
Type:
Grant
Filed:
August 18, 1997
Date of Patent:
April 28, 1998
Assignee:
International Business Machines Corporation
Inventors:
Amir Herzberg, Hugo Mario Krawczyk, Shay Kutten, An Van Le, Stephen Michael Matyas, Marcel Mordechay Yung