Abstract: A method and apparatus for intercepting calls within a wireless communications system. In particular, the present invention provides a call intercept component and a number of control points. Each of the control points is associated with a layer or component within the wireless communications system that handles messages associated with a mobile station within the wireless communications system. Each control point monitors messages received at the component or layer associated with the control point. The messages are examined to determine whether the message is appropriate for interception. If the message is appropriate for interception, the message is then sent the call interception layer. In turn, the call interception layer formats data from the message and routes it to a destination.

Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.

Abstract: Print support may be added to a software component forming part of an existing application by checking the component to determine if it belongs to a class for which print support was originally available. The component may belong to a class having print support available but fail to specifically address print support in its coded methods, or it may belong to a class for which print support was not intrinsically available. If the component belongs to the requisite class, print support may be wired in by simple adding a "dip" component to the subject components' notification methods. The "dip" component provides the necessary dialogs and interfaces to the available print support. If the component is not dippable, or capable of keeping track of dip components, it may be morphed into a dippable component by instantiating a subclass component having the same properties, events, and methods as the undippable component as well as code for keeping track of a dip component.

Abstract: In a processor employing separate instruction and data caches in at least one cache hierarchy level, a cache control instruction forces modified data within the separate data cache to a lower cache hierarchy level. An existing cache access attribute is employed to distinguish between occasions when the data must be written all the way to main memory and occasions when the data need only be written to a cache hierarchy level from which fetches are made to the separate instruction cache. Thus, the separate instruction and data caches may be made coherent without writing all the way to main memory, but the ability to write modified data to main memory whenever necessary is preserved. Utilization of the existing attribute avoids increasing processor complexity and/or resources.

Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces, isolating controller logic from specific architectural complexities. Controller logic may thus be readily duplicated to extend a nonshared cache controller design to a shared cache controller design, with only straightforward modifications required. Throttling of processor-initiated operations handled by the same controller logic resolves operation flow rate issues with acceptable performance trade-offs.

Abstract: In a data processing system with built in audio capability, audio setup instructions are provided. Delivery of the instructions begins after the system is plugged in. Once a video connection has been established, the audio instructions may be supplemented with directly relevant visual information. The object of each instruction may be tested for successful completion. Additional instructions and information may be provided, or optional instructions and information skipped, depending on the requirements of the individual setup.

Abstract: When a speech signal that may include a sibilant consisting of one or more formants is received, frequencies and selectivity factors are determined for each sibilant formant in the speech signal. Then, the frequencies and selectivity factors are compared to a set of empirically derived criteria to classify the sibilant sound.

Abstract: Scroll bars conventionally used in a graphical user interface are replaced with "more" bars at each edge of a display bordering a direction in which more information is available for viewing. Actuation of a cursor on one of the more bars scrolls the display in the direction of the more bar. The more bars provide an intuitive mechanism for controlling the display of graphical user interface.

Abstract: A method and system of increasing efficiency within a data processing system having multiple applications executing within the data processing system. Each of the applications requires a specific environment. A collection of parameters which specify an environment is stored within the data processing system in response to an initialization of the environment for utilization by a first application. Next, the minimal requirements of an second application requesting an environment are determined in response to an attempted initialization of the second application. An existing environment is then utilized if the collection of parameters specifying the environment meets the minimal requirements of the second application, wherein data processing efficiency is increased.

Abstract: Logical drive letters are assigned to a peripheral device in a computer using stored identifying information and a corresponding preferred drive letter assignment for each peripheral device having a preferred drive letter assignment. During system initialization, identifying information--a physical device specifier or a logical volume identification--is obtained from the peripheral device. This identifying information obtained from the peripheral device is compared to similar stored identifying information. If a match is found, the peripheral is assigned the corresponding preferred drive letter, if possible.

Abstract: An enhanced PCI bus architecture utilizing differential signaling is supported by an adapter slot connector providing differential signaling pins and a make-before-break connection between bus conductors and dummy loads for each bus conductor, enabling higher frequency and higher bandwidth operation. The dummy loads simulate the signal load of an adapter inserted into the slot. The PCI bus conductors are automatically disconnected from the dummy loads and connected to the adapter pins when an adapter is inserted into the slot. A balanced load bus is thus provided regardless of whether adapter slots are populated or empty.

Abstract: A nonvolatile memory is provided with a counterfeit detection mechanism by storing an encryption key and performing cryptographic operations on chip. The encryption key, which is stored in the nonvolatile memory in a protected manner such that it is never exported, is based on unique data within the nonvolatile memory. Unless an expected encryption key calculated from the unique data matches the stored encryption key, the system will not allow the resource containing the nonvolatile memory to be utilized. Equivalence of the expected and stored encryption keys is tested by enciphering and deciphering a random number. The data in the nonvolatile memory may be copied but not altered since each data block includes an electronic signature. Modification of the data in the nonvolatile memory as part of an effort to counterfeit the stored encryption key is therefore useless.

Abstract: A method and system for maintaining the integrity of shared files when products are removed and restored. At least two programs, a first program and a second program, within the data processing system share a data structure. A profile is created for the data structure that is shared by the first and second programs. The first program is removed from the data processing system. The shared data structure altered using the profile such that the second program remains on the data processing system unaffected by the alteration of the shared data structure, wherein programs within the data processing system are efficiently maintained.

Abstract: A process for use in a data processing system to define a display area within a display device in the data processing system. The display device includes an unviewable portion and a viewable portion in which a plurality of borders define the viewable portion of the display. The process includes displaying a line or some other graphical object parallel to the border within the plurality of borders in the display device. The line is moved relative to the border in response to a user input wherein the line remains parallel to the border. The line is fixed in response to a second user input. Additional lines are displayed, moved, and fixed for the remaining borders forming the viewable portion of the display, resulting in the definition of a display area. This display area is stored and employed to display data on the display device such that data is not displayed in the unviewable portion of the display device.

Abstract: In a data processing system including a system bus supporting memory mapped devices, dynamic response to a memory mapped command is achieved by receiving a status response from each device attached to the system bus and comparing a priority associated with each such status response to a predetermined priority. If a priority associated with the status response from one of the devices equals or exceeds the predetermined priority, indicating that the address in the memory mapped command is acknowledged in some form by that device, the status response from that device is forwarded to all devices attached to the system bus. If no status response received from the devices has an associated priority equalling or exceeding the predetermined priority, the address is acknowledged and the memory mapped command accepted and forwarded to a lower bus. If the memory mapped command is not accepted by the lower bus, dummy data is returned and a machine check is signaled.

Abstract: A digital data waveform precompensated for off-chip cable attenuation includes peaks with exponential tails at signal transitions. A driver output stage generating the waveform includes an output transistor pulling the output to a peak voltage level when an input goes high. After a delay, a transistor closes a feedback loop containing a resistive load, exponentially changing the voltage level of the output to a final voltage level. A complementary output transistor pulls the output to a ground voltage level when the input goes low, with a transistor closing a feedback loop containing a resistive load for exponential change of the output to a final voltage level. The separate resistive paths equalize the time constant of the exponential tails despite a difference in the gate capacitances of the output transistors. The received waveform after cable attenuation exhibits pulse shapes closer to the predefined pulse shapes on which a receiver is designed to operate.

Abstract: The performance of a DASD having a data cache and at least one set of R/W heads is improved by implementing a replacement policy which, upon determining that a request for data in the DASD requires replacement of a data in a data cache buffer, selects cache data corresponding to data which is cheapest to retrieve from the DASD in view of a location of the DASD R/W heads and replaces the selected cache data with the requested data, thus keeping the cache filled with data which is least expensive to retrieve from the DASD. Data in the DASD is updated from the cache when it is inexpensive.

Abstract: A method and system for managing events within a calendar program executing within the data processing system. Selected events are associated with each other. An action is performed on the selected events in response to a completion of one of the selected events. The action performed may be marking the selected events as being completed or deleting the selected events. Similar actions may be performed on the selected events in response to a deletion of one of the selected events.

Abstract: A L2 cache for resolving collisions between processor request originating from a processor and system request originating from a computing unit attached to the system bus is provided. First, the L2 cache snoops a system request to access a shared resource. This shared resource is often an area of main memory contained in the L2 cache. Next, the L2 cache receives a processor request to access the shared resource also. The L2 cache will delay sending an acknowledge signal to the processor. The L2 cache then makes a determination as to whether the address and system request type must be sent to the processor. If data associated with the system request would alter a line in a L1 cache associated with the processor, a retry signal is sent to the processor. If the system request would not alter a line in the L1 cache, the L2 cache will wait until the system request finishes accessing the shared resource to process the processor request, thereby avoiding the sending of a retry signal to the processor.

Abstract: Instructions are efficiently scheduled for execution based on a stored identification of the first processor cycle when a result of a previous instruction required as an operand for the instruction to be scheduled will become available. Examination of stored processor cycle identifications for the operands of an instruction reveals the earliest processor cycle when the instruction may be executed. By selecting the greater of the largest stored processor cycle identification for an operand of the instruction and the earliest available processor cycle for an execution unit required to execute the instruction, the instruction is efficiently scheduled for the earliest possible execution. Latency of previous instructions in generating an operand of the instruction being scheduled is automatically accommodated.