Abstract: An algorithmic pattern generator for generating an output vector on each pulse of a clock signal includes a vector memory for storing a vector and an accompanying repeat number at each of several addresses. On each of N consecutive clock signal pulses, a repeat processor appends an instance of a vector read out of the vector memory to the pattern generator's output vector sequence. An instruction processor causes the instruction memory to read out instructions and responds to each instruction by telling the instruction processor to signal the address counter to supply the starting address to the vector memory and to thereafter periodically increment the starting address for M consecutive clock signal cycles. When appending N instances of each vector to the pattern generator output sequence, the repeat processor inhibits the address counter from incrementing its output address for N−1 cock signal cycles.
Abstract: A switch for routing input signals from any of N input terminals to one or more of M output terminals includes a high-speed N×M crosspoint switch array providing the necessary signal paths. Each of a set of N input drivers buffers a separate one of the input signals into the crosspoint array and each of a set of M output drivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array is horizontally and/or vertically segmented by input and output buffers to limit the amount of the array's capacitance that each input driver must charge and discharge when the input signals change state, thereby reducing signal path delay through the crosspoint array.
Abstract: Each object (such as for example an integrated circuit) of a population of similar objects is configured to generate instances of a dynamic binary identification code (ID) that differ from instances of IDs generated by all other member objects of the population. While bits residing in most of the bit positions of the ID generated by each member object of the population do not vary in state from instance-to-instance of that ID, bits residing in one or more of the bit positions of the ID may vary (drift) in state from instance-to-instance of that ID. A set of instances of the ID generated by each member object of the population are analyzed to construct a separate “drift profile” for each member object's ID indicating for each bit position a probability that the bit position will contain a bit of a particular state.
Abstract: An IC layout tool determines areas of an IC layout in which to provide power wire interconnection vias by first querying a “world” HV tree keeping track of power wires and other objects within the IC layout to determine areas of overlap between power wires residing on differing layers of the layout. The layout tool then creates a separate via HV tree identifying positions of “via boxes” residing on areas of each layer of the IC between overlapping power wires. The tool manipulates the data stored in the via HV tree to partition and merge adjacent via boxes residing on each layer as necessary to produce via boxes indicating positions of a set of unobstructed, rectangular areas of each layer of the layout in which vias may be placed to interconnect overlapping power wires. The IC layout tool then places vias in each rectangular area of each layer the via HV tree indicates is being occupied by via boxes.
Abstract: A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.
August 29, 2002
Date of Patent:
August 24, 2004
Cadence Design Systems, Inc.
Jui-Ming Chang, Chin-Chi Teng, Wei-Jin Dai
Abstract: An integrated circuit (IC) layout process is organized into two phases. During the Phase 1 of the process, a preliminary placement plan is generated fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is also generated establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets various signal path timing, signal integrity, and power distribution and other constraints. Thereafter, at the start of Phase 2 of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the exact routes to be followed by all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.
August 12, 2002
Date of Patent:
August 24, 2004
Cadence Design Systems, Inc.
Mitsuru Igusa, Shiu-Ping Chao, Wei-Jin Dai, Dennis Huang
Abstract: A high-speed, low distortion N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals. The crosspoint switch includes a switch cell array having N rows and M columns of switch cells. Each of N input lines convey the input signal arriving at a separate one of the N input signals to each switch cell of a corresponding array row. Each of M output lines convey output signals generated by cells of a corresponding array column to a separate switch output terminal. Each switch cell contains a CMOS tristate buffer and a memory cell for storing data controlling whether the tristate buffer is active or inactive. When a tristate buffer is active, it buffers an input signal appearing on one of the input lines to generate an output signal on one of the output lines. When inactive, a tristate buffer refrains from generating an output signal in response to its input signal.
Abstract: A clock tree synthesizer alters a clock tree design to balance a clock tree receiving and distributing one or more clock signals to many clocked devices (“sinks”) within an integrated circuit, wherein the clock tree includes one or more crossover and reconvergence points at outputs of multiplexers receiving clock signals via different paths through the clock tree. The clock tree synthesizer balances the clock tree by first balancing the subtree downstream of each multiplexer and then representing the multiplexer and the subtree with a separate macro for each multiplexer input, each macro representing the path delay from the corresponding multiplexer input to the sinks receiving clock signal inputs via the subtree. When the clock tree includes crossover points, the macros split the clock tree into a separate tree for each clock signal.
Abstract: A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate. The base level partitions include syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition. In accordance with the method, a plurality of independently balanced subtrees are separately synthesized. Each subtree resides within the area occupied by a separate base level partition and includes a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area. Thereafter a top level portion of the clock tree is synthesized.
Abstract: A database system accesses database records referenced by a binary number key having two fields, a typeID field containing only deterministic bits, and a uniqueID field permissibly containing one or more non-deterministic bits at any bit positions therein. The database system maintains a set of databases, each being identified by a separate value of the typeID field of the binary number key. The records of each database are allocated among a plurality of bins, with each bin being identified (keyed) by separate value of a binID field, and with each record being identified (keyed) by a separate value of a recID field. The database system locates a record of interest referenced by the binary number key by first selecting a particular one of the databases that is identified by the typeID field of the binary number key.
Abstract: A relay includes one or more conductive coils embedded in a substrate having multiple insulating layers. Each coil is formed by conductive traces formed between several substrate layers and vias extending vertically between traces on adjacent layers. Each coil surrounds a separate core extending vertically within the substrate. At least one set of contacts reside on the substrate bordering a space containing a contactor. The contactor is formed of conductive material, has a conductive surface and is “free-floating” in that it is unattached to any other object and free to move within the space bordered by the contacts. Current passing through the coil or coils produces magnetic fields which can move the contactor onto or away from the contacts so as to selectively make or break a signal path between the contacts.
Abstract: An analog-to-digital converter (ADC) includes N stages implemented within a single integrated circuit and connected in series to form a pipeline. The first stage of the pipeline receives the analog signal as its input, and each of the first N−1 stages of the pipeline supplies an analog residue signal as input to a next succeeding stage of the pipeline. Each stage includes an amplifier for amplifying its input signal to produce a sample voltage stored in an internal sampling capacitor and generates output data indicating an approximate magnitude of its stored sample voltage. The magnitude of the analog residue signal produced by each stage indicates a difference between the voltage represented by that stage's output data and its sample voltage.
Abstract: A traffic manager for a network switch port stores incoming cells in a cell memory and later forwards them out of the cell memory and the switch port. Each cell is assigned to one of several flow queues and each flow queue has an assigned minimum forwarding bandwidth with which cells of that flow queue must be forwarded from the cell memory and has an assigned maximum bandwidth with which cells of that flow queue may be forwarded. When any flow queue is active (i.e., when it has cells currently stored in the cell memory), the traffic manager allocates a sufficient amount of the switch port's available cell forwarding bandwidth to each active flow queue so that cells of that flow queue are forwarded with at least the flow queue's assigned minimum bandwidth.
Abstract: A relay controller intermittently connects a power supply across a relay coil with a controlled duty cycle whenever the relay coil is to generate a magnetic field for opening or closing the relay's contacts. The duty cycle with which the controller connects the power supply across the coil controls limits a steady-state amplitude of current passing through the coil, thereby controlling the intensity of the magnetic field the coil generates.
Abstract: To help eliminate overlapping cell placements or to reduce routing congestion in an IC layout wherein cells are integer multiples of a standard size cell unit, the layout is organized into an array of rectangular blocks, each having capacity to accommodate several cell units. A separate equation is established for each block relating a sum of a set of flow variables to an “overflow factor”. Each flow variable of the equation for each block corresponds to a separate one of that block's neighboring blocks and represents an estimated number of cell units that must be moved to or received from the corresponding neighboring block to eliminate overlapping cell placements or routing congestion within the block. The overflow factor for each block represents an estimated total number of cell units the block must pass into its neighboring blocks or an estimated maximum number of cell units it may receive from its neighboring blocks in order to eliminate cell overlap or routing congestion in all blocks.
Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.
October 30, 2001
Date of Patent:
November 18, 2003
Cadence Design Systems, Inc.
Wei-Jin Dai, Kit-Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao
Abstract: An analog signal is digitized by an analog-to-digital (A/D) converter clocked by a periodically jittery clock signal. Elements of the digital data sequence (vector) output of the A/D converter are sorted into a set of smaller vectors according to clock signal jitter phase and each of the smaller vectors is then separately subjected to Fourier transform and time shift functions. The resulting vectors are then processed to produce an output vector representing the frequency spectrum of the analog signal.
Abstract: A sigma-delta circuit converts an analog or digital input sequence xn representing a quantity with at least p-bit resolution into an m-bit output sequence yn, where m<p<0. The sigma-delta circuit offsets the xn sequence by a first feedback sequence cn that is proportional to output sequence yn to produce a sequence an. The signal-delta circuit filters the an sequence using a filter having a transfer function H(z−1) to produce a sequence dn that is offset by a second feedback sequence rn to produce an analog or digital sequence bn. The bn sequence is then digitized or quantized to produce the lower resolution m-bit output yn sequence.
Abstract: A network switch for routing data between network stations includes a set of input ports for receiving data transmissions from network stations, a set of output ports forwarding data transmissions to network stations and a crosspoint switch for routing data transmissions from each input port to a selected output port. When an input port receives a data transmission it sends a request to a routing arbitrator requesting a connection through the crosspoint switch to an output port that is to forward the transmission to a network station. A routing arbitrator grants a connection request commanding the crosspoint switch to establish a data path from the requesting input port to the requested output port. Each output port stores each data transmission received from an input port in a data buffer until it can forward that data transmission to a network station.
Abstract: A 100Base-TX receiver employs a finite impulse response (FIR) filter to provide both equalization and insertion loss compensation for an MLT-3 input signal. The FIR filter includes three delay stages, each delaying the input signal with an 8 ns delay (the period of one data cycle of the MLT-3 input signal), a set of three amplifiers for amplifying the delay stage outputs with gains C1, C2 and C3, and a summer for summing the outputs of the three amplifiers to produce a compensated, equalized MLT-3 signal. A low-pass filter filters the FIR filter output signal, and a data slicer digitizes the low-pass filter output during each data cycle to produce data representing the incoming MLT-3 as having one of six levels. An adaptive control signal processes the slicer output data to determine how to set the gains C1, C2 and C3 of the three FIR amplifiers to provide the correct amount of equalization and compensation.