Abstract: A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory.

Abstract: A system for determining scattering parameters (S-parameters) characterizing the behavior of a network applies a wideband stimulus signal containing multiple signal components as input to the network. The system then measures incident and reflected waveforms at all of the network's ports, digitizes and converts the measured waveforms from time domain to frequency domain data, and then computes the S-parameters values for each frequency component of interest from the frequency domain data for that frequency. The system also determines its own error coefficients (E-coefficients) for each frequency of interest from data collected during a sequence of measurements in response to either a sinusoid or a wideband signal and adjusts the computed S-parameter values accordingly.

Abstract: A system uses an event based equivalent time sampling method for ascertaining a value of each bit of a data frame repeated in a digital signal of indeterminate phase. The system measures time intervals between rising edges of the digital signal and a reference time and between falling edges of the digital and that reference time in response to pulses of a periodic arming signal. The measured time intervals are then normalized to equivalent time intervals and those intervals analyzed to determine values of each bit of the data frame.

Abstract: A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.

Abstract: When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.

Abstract: An interface system enables conventional software applications running on host computers linked via a network to communicate with in-circuit emulators having component ports accessed through the network. The interface system represents each in-circuit emulator as a separate communication object model (COM) object. Each COM object has a set of interfaces, with each interface including a set of methods for carrying out various in-circuit emulator programming and data transfer functions. To communicate with an emulator, a software application links to an instance of the emulator's COM object and thereafter makes calls to the methods included in the object's interfaces. The system permits an application linking to an instance of an in-circuit emulator's COM object to optionally block other applications from linking to other instances of that COM object to prevent conflicts in control over the in-circuit emulator.

Abstract: A timing signal generator including a direct digital frequency synthesizer (DDFS), a divide-by-N counter, and a pattern generator, produces a TIMING signal conveying a timed sequence of pulses. The pattern generator produces a sequence of data pairs (FREQ,N), with each pair being produced in response to each pulse of the TIMING signal and indicating a time interval that is to occur between that TIMING signal pulse and a next TIMING signal pulse. The DDFS produces an output sine wave signal (SINE) having a frequency controlled by the current FREQ data output of the pattern generator. The divide-by-N counter produces the timing signal pulses. It counts cycles of the SINE signal occurring since it last produce a TIMING signal pulse and generates a next TIMING signal when it has counted the number of SINE signal pulses indicated by the current N data output of the pattern generator.

Abstract: A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics.

Abstract: Disclosed herein is a method for dividing an integrated circuit (IC) design into several circuit partitions, each including one or more circuit modules, and then separately carrying out placement and routing for each circuit partition, with each partition being implemented within a separate area of an IC substrate. The method initially generates a whole-chip trial placement that tends to cluster cells of each circuit module together. An IC substrate floor plan assigning modules to various partitions is prepared, with the size, shape and relative position of each partition being determined by size, shape and relative position of areas of the substrate occupied by those modules in the trial floor plan. A trial routing is also performed with information on which to base a pin assignment plan for each module. A detailed placement and routing process is then independently performed for each partition, with placement and routing of cells within each partition constrained by the floor plan and pin assignment plan.

Abstract: An improvement is provided to a network switch of the type including a set of input and output ports for receiving and forwarding data transmissions from and to network stations and a crosspoint switch for selectively routing data transmissions between the input and output ports. Each input port stores successive incoming data transmissions in an input buffer queue. When a data transmission reaches the head of the queue, the input port requests a route through the crosspoint switch to an output port that is to forward the transmission to a network station. When the output port is ready to receive the transmission the crosspoint switch establishes the route and the input port forwards the data transmission from its buffer queue to the output port. In the improved network switch, the input port discards the data transmission at the head of the buffer queue without forwarding it to an output port when necessary to make room in the buffer for incoming transmissions.

Abstract: A crosspoint switch includes a large number of ports and a separate pass transistor linking each possible pair of ports. When a pass transistor is turned on or off, it makes or breaks a signal path between the pair of ports it links. Each port can process signals passing through the port in any one of several operating modes, with a current operating mode being selected by input mode control data. The crosspoint switch also includes a random access memory (RAM) having a separate addressable storage location corresponding to each port. Each RAM storage location stores routing data for controlling the pass transistors connected to a corresponding port and also stores mode control data controlling the mode of the corresponding port. A memory controller responds to a parallel command from a host computer by concurrently writing routing and mode control data to two storage location of the RAM, thereby quickly making and/or breaking a signal path between two ports and selecting the operating mode of both ports.

Abstract: A system for testing a set of integrated circuits (ICs) that may be implemented as dies in a group of wafers or as packaged ICs mounted in a group of load boards includes a test head for testing the ICs and a prober or handler for holding each wafer or load board with the IC in electrical contact with the test head so that it may be tested. The test system employs a host computer to coordinate activities of the test head and the prober or handler. Software executed by the host computer is partitioned into a device interface function library (DIFL) for communicating with the prober or handler and test head control program for communicating with the test head and for indirectly communicating with the prober or handler by making function calls to the DIFL.

Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

Abstract: Modules of a network switch receive data transmissions from network stations via its I/O ports, each data transmission including an address of a source network station sending the transmission and an address of a destination station to receive the transmission. Each module receiving a data transmission either passes it on to a next module of the network switch via a ring bus or forwards it to the destination station when it is accessible via one of the module's own I/O ports. Each module includes an address translation unit mapping the network address of each station to the particular I/O port though which that network station communicates. The address translation unit updates its address-to-port mapping when a data transmission arrives at an I/O port from a source station having an unmapped or incorrectly mapped address, and then sends a mapping instruction to address translation units of all other switch modules via the ring bus telling them to similarly update their network address mappings.

Abstract: Variation in temperature of a digital logic circuit that temporarily increases its heat production after a digital input signal changes state is limited using a heater that applies heat to the digital logic circuit at a variable rate. A control circuit monitors all of the circuit's digital input signals and temporarily decreases the rate at which the heater applies heat to the digital logic circuit after each state change in a digital input signal. The amount of temporary reduction in heater output is sized to substantially match the amount of temporary increase in logic circuit heat production so that the temperature of the logic circuit remains largely unaffected. A feedback circuit is also provided to monitor the temperature of the digital logic circuit and to further adjust the heater output so as to help maintain the logic circuit at a desired temperature.

Abstract: A document assembly system assembles and prints one or more documents in response to input data describing the nature and circumstances of a transaction to be documented and describing the parties to the transaction. The document assembly system initially produces a separate document definition object for each document to be produced and a separate party definition object for each party to the transaction. The document definition object includes procedures for generating “document-related” text that a document may use when referring to itself. The party definition object includes procedures for generating party-related text that the document is to use when referring to a party. The nature of the text each document definition or party definition object procedure produces depends on the nature of the document or the party as indicated by the input data.

Abstract: In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic discharge (ESD) protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. Also the ESD protection function is distributed among multiple ESD devices interconnected by series inductors to provide a multi-pole filter at each IC terminal.

Abstract: A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUT's increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

Abstract: In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. The inductances of the conductors and various capacitances of the interconnect system are also appropriately adjusted to optimize desired interconnect system frequency response characteristics.

Abstract: A clock signal generator produces an output clock signal having signal pulse timing adjustable with a resolution of P seconds. To produce a clock signal having an average frequency that is other than 1/k*P, where k is an integer, the clock signal generator occasionally adjusts the period between successive pulses of the clock signal.