Abstract: A system for providing concurrent access to an addressable memory space by a plurality of data processing devices includes a plurality of independently accessible memory banks, each memory bank providing a separate portion of the addressable memory space. A memory management unit includes address and data multiplexers corresponding to each memory bank for providing access by any selected one of the data processing devices to the corresponding memory bank and also includes circuits for controlling the multiplexers to permit different processing devices to access different memory banks at the same time while arbitrating competing demands for the same memory bank.

Abstract: A time base circuit for a waveform sampling system produces a strobe signal for initiating waveform sampling an adjustable strobe delay time following detection of a triggering event in a waveform. The time base circuit includes a strobe control circuit for producing the strobe signal and a strobe sense signal in response to a strobe drive signal, a strobe drive circuit for generating the strove drive signal, an adjustable time after a trigger signal, and a trigger generator for producing the trigger signal in selective response to either the triggering event in the waveform or the strobe sense signal. The strobe signal delay time is calibrated by setting the trigger generator to produce the trigger signal in response to the strobe sense signal thereby causing the strobe drive circuit to generate the strobe drive signal periodically.

Abstract: A tristate output circuit includes a pair of transistors having sources connected to a switchable current source and drains separately coupled to a voltage source through separate resistors and switching transistors. When the current source and switching transistors are on, the circuit operates in a back termination mode wherein it amplifies a differential input signal applied across the gates of the transistor pair to produce a differential output signal across their drains for transmission on a transmission line. The load resistors are sized to match the characteristic impedance of a transmission line so as to properly terminate the transmission line. In an open drain mode, the switching transistors are off, uncoupling the drains of the transistor pair from the voltage source so as to increase output impedance. In a tristate mode, the current source and switching transistors are turned off, thereby turning off the transistor pair and rendering the output impedance of the circuit substantially infinite.

Abstract: A digital oscilloscope processes digitized input waveform data sequences according to a user defined mathematical expression to compute a processed waveform data sequence controlling a periodically updated waveform display on a screen. The waveform data is computed during equivalent time computation passes during each of which pass every Nth data of the waveform data sequence is computed. The first waveform data computed during each pass is selected in a pseudorandom fashion such that each data of the waveform data sequence is computed once every N computation passes. The value of N is suitably chosen so that the duration of each pass is substantially equal to the period between waveform display updates.

Abstract: An output stage for producing a high accuracy differential output signal includes a first differential amplifier providing a pair of single-ended first signals of magnitudes that swing in opposite directions between first and second levels following a change in level of an input signal. A sum of magnitudes of the first signals is controlled by an input control current. The first signals provide input to a second differential amplifier supplying a pair of single-ended second signals swinging in opposite directions between third and fourth levels when the first signals change levels, the second signals forming the differential output signal of the output stage. An indicating signal, provided by the second differential amplifier, supplies a measure of a sum of magnitudes of the second signals. A third differential amplifier produces the control current of magnitude determined by a magnitude difference between the indicating signal and a constant reference signal.

Abstract: An apparatus for generating a trigger signal in response to a selected pattern of events includes event synchronizers for generating synchronized event signals of states indicating the current state of each event on the falling edge of each pulse of a clock signal. A programmable encoder provides a set of event encoding signals of states set according to selected patterns of synchronized event signal states. A set of bus drivers actively drives the potential of each conductor of a bus high on the falling edge of each clock signal pulse and actively drives the potential of selected conductors of the bus low on the rising edge of each clock signal pulse, the conductors being selected according to the pattern of event indicating signal states generated by the encoder.

Abstract: A level detecting waveform digitizer for repetitively sampling an analog waveform and converting analog samples into representative digital data is provided with a predictive time base circuit for accurately controlling sample timing with respect to a triggering event in the input waveform and a comparator for indicating when the magnitude of the waveform as indicated by the digital data exceeds a predetermined level. The digitizer also includes a counter for counting samples taken and a second comparator for indicating when the sample count reaches a predetermined limit.

Abstract: A delay circuit generates an output signal that changes state in adjustably delayed response to a state change in an input signal, the delay being adjusted by a control signal. A series of buffers produces a plurality of delayed signals that change state at different times in response to state changes in the input signal. Amplifiers amplify the input and each delayed signal to produce output currents that are summed to provide a load current through load resistors, thereby providing the output voltage across the load resistors. The gain of each amplifier is adjusted in accordance with the control signal such that at least one and not more than two of the amplifiers have non-zero gain. The delay provided by the delay circuit is determined by the relative gains of the amplifiers.

Abstract: A delay element for producing an output signal in response to a change in state of an input signal includes variable gain first and second amplifiers and a delay buffer having a fixed delay. The input signal is applied as input to the first amplifier and the delay buffer while the output of the delay buffer is applied as input to the second amplifier. The outputs of the first and second amplifiers are summed to provide the output signal. When the gain of the first amplifier is high and the gain of the second amplifier is low, the output signal will respond to the change in state of the input signal with minimum delay. When the gain of the first amplifier is low and the gain of the second amplifier is high, the output signal will respond to the change in state of the input signal with maximum delay.

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Abstract: An apparatus for generating trigger signals responsive to a selected pattern of event detection signals, the apparatus comprising an interim function bus, programmable means to selectively energize conductors of the interim function bus on detection of the selected event detection signal pattern, and programmable means to generate the trigger signal on detection of a selected pattern of interim function bus signals. The generating means are programmed for pattern recognition by binary data appearing on control lines from a shift register, the shift register being loaded by serial data from external control circuits. The apparatus also includes provisions for synchronizing the generation of signal patterns on the interim function bus to a system clock, and for synchronizing the generation of trigger signals to clocks associated with triggerable devices.

Abstract: A hand-held inertial mouse provides input data to a computer from which the computer can determine the translational and angular displacement of the mouse. The mouse includes accelerometers for producing output signals of magnitudes proportional to the translational acceleration of the mouse in three non-parallel directions. Pairs of these accelerometers are positioned to detect acceleration along each axis of a cartesian coordinate system such that an angular acceleration of the mouse about any axis of rotation causes representative differences in the magnitudes of the output signals of one or more of these accelerometer pairs. The translational velocity and displacement of the mouse is determined by integrating the accelerometer output signals and the angular velocity and displacement of the mouse is determined by integrating the difference between the output signals of the accelerometer pairs.

Abstract: A platform supporting an electronic device above a work surface, the platform being mounted on a carrier or trolley that is movable between two or more work stations on an elongate base having a track on which the trolley travels. The platform is attached to the trolley by a mounting head that provides tilt and rotation of the platform, and the height of the base above the work surface is adjustable.

Abstract: A current mirror includes first and second transistors having interconnected bases and having emitters respectively coupled through first and second resistors to a common potential source. A collector voltage of the first transistor is fed back to the transistor bases through a feedback capacitor, and through a unity gain amplifier and series resistor, to form a feedback loop for controlling the voltage at the transistor bases. A current source connected to the collector of the first transistor causes the second transistor to produce an output collector current substantially equal in magnitude to the input current. To prevent circuit instability, the feedback capacitor and the aforementioned series resistor are sized to reduce the frequency at which the open loop gain of the feedback loop is unity so that it does not exceed the short-circuit current gain-bandwidth product of the first transistor.

Abstract: For an oscilloscope capable of simultaneously displaying a plurality of waveforms on a screen and capable of performing operations with respect to a selected one of the displayed waveforms, a method and apparatus for permitting an operator to select a waveform. A touchscreen mechanism provides input signals to the oscilloscope indicating when and where an operator touches the surface of the screen and a microcomputer within the oscilloscope determines from data controlling the display of each waveform and from the data provided by the touchscreen whether the operator is touching any portion of a displayed waveform. If so, the microcomputer assumes that the operator has selected the waveform touched and reconfigures oscilloscope operation such that operations are performed with respect to the waveform touched by the operator.

Abstract: A digitizer system includes M digitizers, each producing a separate waveform data sequence representing a succession of instantaneous magnitudes of an input signal at sample times determined by a periodic clock signal. Transmission of the clock signal to each digitizer is delayed by a corresponding adjustable delay time so as to control the relative sample timing of the digitizers. To adjust sample timing, a sine wave signal is applied as the input signal to each digitizer such that the M digitizers produce M separate waveform data sequences in response to said input signal and the M data sequences are interleaved and windowed to form a single waveform data sequence. A first sequence of complex numbers representing a discrete Fourier transform of the single waveform data sequence is generated and then a second sequence of M complex numbers is formed from elements corresponding to relative magnitude peaks of the first sequence.

Abstract: A voltage controlled, triggered oscillator includes a NAND gate and a set of series connected triggerable delay circuits, the output of the NAND gate being fed back to one of its inputs through the delay circuits. A trigger signal is applied to another input of the NAND gate and to triggering inputs of the delay circuits. When the trigger signal is asserted, each delay circuit produces an output signal of state which tracks the state of its input signal but with a predetermined delay so that the NAND gate output oscillates with a frequency determined by the delay times of the delay circuits and the propagation time of the NAND gate. When the trigger signal is deasserted the NAND gate output is terminated and each delay circuit drives its output signal high regardless of the state of its input signal so that the oscillator may be rapidly retriggered.

Abstract: An apparatus for displaying the display outputs of a plurality of simultaneously active computer processes in corresponding windows on a single screen includes a microcomputer, a display screen and display system software. The software represents a plurality of virtual terminals, one corresponding to each active process, for emulating the operation of real terminals communicating with the processes. Each virtual terminal maintains a display list comprising a set of instructions defining a display on a screen according to the output from the corresponding process. The software also includes a screen process for maintaining a subrectangle list comprising a set of instructions for allocating window portions of the screen to the displays defined by the separate display lists. A display list processor is provided for creating the windows on the screen according to the display and subrectangle lists.

Abstract: A pulse generator utilizes a pair of current sources acting through a pair of Schottky diode switches to provide load currents in opposite directions through a load resistor to produce an output voltage across the load resistor of magnitude proportional to the difference between the load current magnitudes. The pulse generator output voltage is abruptly driven to zero potential by applying balanced, rapid slewing voltage pulses to the Schottky diode switches, causing the switches to simultaneously divert the load currents from the load resistor. The balanced voltage pulses are developed at the terminals of a step-recovery diode by switching the step-recovery diode from forward to reverse bias state.

Abstract: A data compression circuit has a compression mode of operation where it determines and stores minimum and maximum values of successive sequences of applied data words and provides an output comprising a pair of data words representing the stored minimum and maximum for each sequence, offset by a selected amount. The circuit also has a transparent mode of operation where output data sequences match input data sequences.