Patents Represented by Attorney, Agent or Law Firm David E. Steuber
  • Patent number: 6350110
    Abstract: The present invention is directed to a multiport metering pump that can completely deliver a very small volume of liquid. The multiport metering pump includes a number of ports (or valve units), each of which can be used as either an outlet valve or an inlet valve. The multiport metering pump includes: a central gallery; a displacement unit; multiple valve units; and multiple conduits that respectively connect the displacement unit and the valve units to the central gallery. The displacement unit and the valve units communicate with the central gallery, and any of the valve units can be used as an inlet valve or outlet valve for the liquid delivery.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: February 26, 2002
    Assignee: B&G International
    Inventor: Kirk Alan Martin
  • Patent number: 6348712
    Abstract: A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: February 19, 2002
    Assignee: Siliconix Incorporated
    Inventors: Jacek Korec, Mohamed N. Darwish, Dorman C. Pitzer
  • Patent number: 6343793
    Abstract: A rotary union for use with an electroplating apparatus includes a shaft having a first surface area and an extended surface area, the first surface area having a first aperture therein, the extended surface area having a second aperture therein. The rotary union further includes an outer face seal and an inner face seal. The outer face seal is pressed against, and forms a seal with, the first surface area. The inner face seal is pressed against, and forms a seal with, the extended surface area. A pressure passage coupled to the first aperture passes through the outer face seal and around the outside of the inner face seal. A pressure/vacuum passage coupled to the second aperture passes through the inner face seal.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: February 5, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Evan E. Patton, Wayne Fetters
  • Patent number: 6343698
    Abstract: A clarifier feedwell having a seismic protection system. The clarifier feedwell includes a feedwell frame and at least one pressure relief door which is slidably inserted into the feedwell frame. The pressure relief door includes a supporting frame, the supporting frame defining an opening. A flexible panel is disposed in the opening. A first edge of the panel is attached to a first portion of the supporting frame. The remaining edges of the panel are releasably engaged with other portions of the supporting frame such that the panel occupies substantially the entire area of the opening. At least one stiffening frame is disposed on the panel. The stiffening frame increases the rigidity of the panel, so that the panel does not disengage from portions of the supporting frame under a normal hydrodynamic load.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: February 5, 2002
    Inventors: Ba T. Than, Ann E. Farrell, William E. Brennan, Kenneth S. Clark, Munawar Husain, Gary A. Aron, Kevin H. Monroe
  • Patent number: 6340958
    Abstract: An information display system comprises a controller, a ceiling node, a rail, an end cap and a solar powered display module. The display module stores and displays information. The controller communicates with the end cap through an IR downlink and an RF uplink, and the end cap communicates with the display module by wired communication. By uniquely combining RF and IR communication systems in the information display system, communication between the controller and the module is fast and accurate and the display module's power consumption is significantly reduced to make a solar powered information display system practical. By a unique power bus, excess power is shared.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: January 22, 2002
    Assignee: PricePoint, Incorporated
    Inventors: Gary R. Cantu, James W. Pfeiffer, Daniel B. Steinberg
  • Patent number: 6328497
    Abstract: A ring for mounting on a carrier mechanism of a binder is disclosed. The ring includes a first ring element and a second ring element. The first ring element includes a first ring element bottom section, which is connected to the carrier mechanism, and a first ring element top section. The first ring element top section includes a first end and a second end. Similarly, the second ring element includes a second ring element bottom section, which is connected to the carrier mechanism, and a second ring element top section. The second ring element top section includes a first end and a second end. The first end of the second ring element top section is joined to the second ring element bottom section, while the second end is adapted for coupling with the second end of the first ring element top section.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: December 11, 2001
    Assignee: World Wide Stationery Manufacturing Co., Ltd.
    Inventor: Chun Yuen To
  • Patent number: 6319842
    Abstract: Non-volatile and oxide residues that form during semiconductor processing are removed from the semiconductor structure in a two-stage process. An inert gas and a reducing gas are introduced to the reactor. In the first stage, the non-volatile contaminants are sputtered from the semiconductor structure by creating a plasma to ionize the inert gas. The power applied to the plasma is preferably high enough to give the ions of the inert gas a high degree of directionality as they approach the structure. The first stage is continued until the non-volatile contaminants have been sufficiently removed from the structure. In the second stage, the power is reduced and the reducing gas (e.g., hydrogen) reacts with the oxides (e.g., copper oxide) to form elemental metal and water vapor. During the second stage there is no appreciable sputtering, and therefore the damage to the structure is limited as compared with processes that use sputtering and reduction simultaneously.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: November 20, 2001
    Assignee: Novellus Systems Incorporated
    Inventors: Mukul Khosla, Lap Tam, Ronald A. Powell, Ronald D. Allen, Robert T. Rozbicki, Erich Klawuhn, E. Derryck Settles
  • Patent number: 6319553
    Abstract: A multi-station processing chamber in which incompatible processes are performed includes multiple pedestals positioned in wells with annular gaps around the pedestals. Showerheads located above the pedestals flow reactive gases over substrates located on the pedestals. The reactive gases are drawn through the annular gaps by a pressure gradient. The reactive gases are then pumped out of the wells through an exhaust port. The narrow annular gap permits little recirculation of the reactive gases one they are drawn into the wells. Moreover, the showerheads are flush with ceiling of the chamber and the wells contain smooth contours to minimize dead space in the chamber thereby reducing residence time of the reactive gases. An indexing plate is used to lift the substrates off the pedestals and to accurately position the substrates at the next processing station.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: November 20, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Edward J. McInerney, Thomas M. Pratt, Shawn D. Hancock
  • Patent number: 6319454
    Abstract: A method and apparatus for manufacturing a hollow plastic product is provided. In accordance with one aspect, into a mold half having a tubular groove portion and a projecting groove portion which projects outwardly from the tubular groove section is supplied a parison into the tubular groove portion and a clump of molding material into the projecting groove portion, and when blow molding is carried out by introducing a pressurized gas into the parison, the clump becomes integrated with the parison thereby providing a plastic product of unitary structure. In accordance with another aspect of the present invention, a parison extrusion nozzle is provided with at least two passages each of which is connected, preferably through a valve, to a corresponding dispensing unit for dispensing a desired molding material. A control unit is provided as connected to each of the dispensing units to control the supply of molding material so that there is obtained a parison having regions of different molding materials.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: November 20, 2001
    Assignee: Excell Corporation
    Inventors: Tatsuya Nakagawa, Yasuo Ezaki
  • Patent number: 6316777
    Abstract: A dual sample-and-hold architecture in each unit cell of a read-in-integrated-circuit (RIIC) provides maximum frame rate without frame overlap. Analog pixel signals are updated sequentially in one sample-and-hold capacitor, while an emitter element displays a pixel of a display frame in response to a stored analog signal voltage on an isolated second sample-and-hold capacitor. After all unit cells are updated, the signals on the two capacitors are combined, updating all emitter elements for the next frame. A voltage mode amplifier as an emitter driver provides a more nearly linear dependence of infrared power output on signal voltage than do previous transconductance amplifiers. A digital to analog converter (DAC) on the RIIC substrate results in a simplified interface to the RIIC and in an increased immunity to noise.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: November 13, 2001
    Assignee: Indigo Systems Corporation
    Inventors: William J. Parrish, Naseem Y. Aziz, Jeffrey L. Heath, Theodore R. Hoelter
  • Patent number: 6307755
    Abstract: A leadframe for making an electric connection to a semiconductor die contains a plurality of notches which correspond to the edges of the die. Shorts are thereby prevented between the leadframe and electrical elements near the edge of the die, even when the leadframe is bent in the direction of the die to make a surface mount package. Alternatively or additionally, the leads in the leadframe may contain moats which prevent the epoxy or solder used to attach the leadframe to a die from spreading outward and thereby creating electrical shorts with other leads.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: October 23, 2001
    Inventors: Richard K. Williams, Allen K. Lam, Alexander K. Choi
  • Patent number: 6300744
    Abstract: Where an AC adapter is used to supply power to both an electronic device such as a notebook computer and a rechargeable battery, as where the computer is turned on while the battery is being recharged, the voltage at the output terminal of the AC adapter is detected and delivered to abattery charger that is used to supply a constant current to the battery. When the current from the AC adapter exceeds its rated current, the voltage at the output terminal begins to fall. When the output voltage falls below a predetermined trigger voltage, the voltage detector instructs the battery charger to limit the current delivered to the battery, and the current is reduced until the voltage at the output of the AC adapter again reaches the trigger voltage. This arrangement provides for a maximum use of the power available from the AC adapter when the combined power demands of the electronic device and the battery exceed the power delivery capability of the AC adapter.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: October 9, 2001
    Assignee: Siliconix Incorporated
    Inventor: Kin E. Shum
  • Patent number: 6296906
    Abstract: Dielectric films in integrated circuits are annealed in the presence of water to improve their thermal stability and their resistance to damage from ultraviolet radiation.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: October 2, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Jim Stimmell, Joe Laia, Ajay Saproo
  • Patent number: 6291298
    Abstract: The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: September 18, 2001
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Wayne B. Grabowski
  • Patent number: 6284121
    Abstract: An electroplating system includes a standard electroplating apparatus using an acid copper bath with an additive for leveling. The additive is chosen to have molecules of a size that is about the size of the features to be filled by the electroplating process. The relatively large size of these additive molecules tends to hinder the mass transfer of the additive molecules into the features. Consequently, the additive molecules are preferentially absorbed by the surface of the plating surface relative to the inner surfaces of the features. Accordingly, the electroplating process tends to fill the features relatively quickly compared to the other parts of the target surface so that all of the surface area of the target is equivalent in height. Because little or no additive molecules are within the features, the features tend to be filled without the voids often produced using conventional systems.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: September 4, 2001
    Assignee: Novellus Systems, Inc.
    Inventor: Jonathan David Reid
  • Patent number: 6285060
    Abstract: In a trench-gated MOSFET, a lightly doped drift region of the N-type drain lies in the mesa between the trenches. The gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero. The depletion regions merge at the center of the mesa, pinching off the flow of current when the device is turned off. This current-pinching effect allows the P-type body region to be made shallower and doped more lightly than usual without creating a punchthrough problem, because the barrier represented by the depletion regions adds to the normal current blocking capability of the PN junction between the body and drain regions. When the device is turned on by biasing the gate to a positive voltage, a low resistance accumulation layer forms in the drift region adjacent the trenches.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: September 4, 2001
    Assignee: Siliconix Incorporated
    Inventors: Jacek Korec, Anup Bhalla
  • Patent number: 6283838
    Abstract: A burnishing tape apparatus includes pads that press the burnishing tape against the surfaces of the disk to be burnished. The pads are mounted on pad holders that are biased to press the pads against both sides of the disk. Tape guides are used to apply tension to the burnishing pad when the pads are moved away from the disk. When the pads are away from the disk tape guides hold the burnishing tape away from the pads so that the burnishing tape may be indexed without damaging or dislodging the pads. As the pads are moved into contact with the disk, the tape guides release the tension on the burnishing tape while the centering guides ensure that the burnishing tape is centered on the pads. By releasing tension on the burnishing tape, the pads are permitted to press the approximate center of the burnishing tape against the surfaces of the disk without deforming in an uncontrolled manner.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: September 4, 2001
    Assignee: Komag Incorporated
    Inventors: Elree Blake, Shaun H. Chen, Daniel K. Walsh, Scott M. Hipsley
  • Patent number: 6281144
    Abstract: A structure and method are provided to exclude polymer film deposition from the backside and edge of a wafer during CVD processing. An electrostatic chuck (ESC), with radial and circular channels and grooves on its surface, secures a wafer to be processed. An inert gas, preferably argon, flows outward from these channels and grooves along the backside of the wafer. A uniform flow of the gas from underneath the wafer into the process chamber prevents monomer molecules from depositing on the wafer backside. For edge exclusion, a showerhead is placed slightly above the outer diameter of the wafer to keep most of the monomer molecules within the process chamber and redirect the remaining monomer molecules across the surface of the wafer below the outer edge of the showerhead.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: August 28, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas J. Cleary, James C. Wing
  • Patent number: 6277695
    Abstract: The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: August 21, 2001
    Assignee: Siliconix Incorporated
    Inventors: Richard K. Williams, Sung-Shan Tai, Dorman C. Pitzer, Wayne B. Grabowski, Anthony Tsui, Mike F. Chang
  • Patent number: 6277235
    Abstract: A processing chamber with a showerhead and a chuck is cleaned using an injection of a gaseous cleaning agent through an aperture in the chuck into the processing chamber. Because the aperture is located directly under the showerhead, a portion of the gaseous cleaning agent passes through the face plate of the showerhead so that the inside of the showerhead may be cleaned as well. By applying a radio frequency power supply between the chuck and the showerhead, for example, by a coil located between the chuck and showerhead or applying the power directly to the chuck and the showerhead, the gaseous cleaning agent forms a plasma. Thus, the portion of the gaseous cleaning agent that passes through the face plate and into the showerhead is a plasma. The plasma is pumped out of the chamber through a pumping port so that the plasma continuously flows through the processing chamber.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: August 21, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: James C. Wing, Edward J. McInerney